From cc6c011443cbbee49d5a536d4c8e5c38ee5c0a21 Mon Sep 17 00:00:00 2001 From: Qiuxu Zhuo Date: Mon, 17 Jan 2022 03:49:34 -0500 Subject: [PATCH] EDAC/skx_common: Fix the DDR5 DIMM size The bus between the memory controller and the DIMM for DDR5 is 32-bit data + 8-bit ECC. Fix the DDR5 DIMM size accordingly. Signed-off-by: Qiuxu Zhuo --- drivers/edac/skx_common.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/edac/skx_common.c b/drivers/edac/skx_common.c index f0f8e98f6efb..9b6c79c882b7 100644 --- a/drivers/edac/skx_common.c +++ b/drivers/edac/skx_common.c @@ -344,7 +344,7 @@ int skx_get_dimm_info(u32 mtr, u32 mcmtr, u32 amap, struct dimm_info *dimm, struct skx_imc *imc, int chan, int dimmno, struct res_config *cfg) { - int banks, ranks, rows, cols, npages; + int banks, ranks, rows, cols, npages, log2_bus_width = 3; enum mem_type mtype; u64 size; @@ -356,6 +356,7 @@ int skx_get_dimm_info(u32 mtr, u32 mcmtr, u32 amap, struct dimm_info *dimm, banks = 32; mtype = MEM_HBM2; } else if (cfg->support_ddr5 && (amap & 0x8)) { + log2_bus_width = 2; banks = 32; mtype = MEM_DDR5; } else { @@ -364,9 +365,9 @@ int skx_get_dimm_info(u32 mtr, u32 mcmtr, u32 amap, struct dimm_info *dimm, } /* - * Compute size in 8-byte (2^3) words, then shift to MiB (2^20) + * Compute size in 8-byte (2^3) or 4-byte (2^2) words, then shift to MiB (2^20) */ - size = ((1ull << (rows + cols + ranks)) * banks) >> (20 - 3); + size = ((1ull << (rows + cols + ranks)) * banks) >> (20 - log2_bus_width); npages = MiB_TO_PAGES(size); edac_dbg(0, "mc#%d: channel %d, dimm %d, %lld MiB (%d pages) bank: %d, rank: %d, row: 0x%x, col: 0x%x\n",