crypto: hisilicon/qm - add UACCE_CMD_QM_SET_QP_INFO support
To be compatible with accelerator devices of different versions, 'UACCE_CMD_QM_SET_QP_INFO' ioctl is added to obtain queue information in userspace, including queue depth and buffer description size. Signed-off-by: Weili Qian <qianweili@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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@ -3430,6 +3430,7 @@ static long hisi_qm_uacce_ioctl(struct uacce_queue *q, unsigned int cmd,
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unsigned long arg)
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{
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struct hisi_qp *qp = q->priv;
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struct hisi_qp_info qp_info;
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struct hisi_qp_ctx qp_ctx;
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if (cmd == UACCE_CMD_QM_SET_QP_CTX) {
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@ -3446,11 +3447,25 @@ static long hisi_qm_uacce_ioctl(struct uacce_queue *q, unsigned int cmd,
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if (copy_to_user((void __user *)arg, &qp_ctx,
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sizeof(struct hisi_qp_ctx)))
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return -EFAULT;
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} else {
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return -EINVAL;
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return 0;
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} else if (cmd == UACCE_CMD_QM_SET_QP_INFO) {
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if (copy_from_user(&qp_info, (void __user *)arg,
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sizeof(struct hisi_qp_info)))
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return -EFAULT;
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qp_info.sqe_size = qp->qm->sqe_size;
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qp_info.sq_depth = qp->sq_depth;
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qp_info.cq_depth = qp->cq_depth;
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if (copy_to_user((void __user *)arg, &qp_info,
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sizeof(struct hisi_qp_info)))
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return -EFAULT;
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return 0;
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}
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return 0;
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return -EINVAL;
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}
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static const struct uacce_ops uacce_qm_ops = {
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@ -14,11 +14,26 @@ struct hisi_qp_ctx {
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__u16 qc_type;
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};
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/**
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* struct hisi_qp_info - User data for hisi qp.
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* @sqe_size: Submission queue element size
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* @sq_depth: The number of sqe
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* @cq_depth: The number of cqe
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* @reserved: Reserved data
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*/
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struct hisi_qp_info {
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__u32 sqe_size;
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__u16 sq_depth;
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__u16 cq_depth;
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__u64 reserved;
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};
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#define HISI_QM_API_VER_BASE "hisi_qm_v1"
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#define HISI_QM_API_VER2_BASE "hisi_qm_v2"
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#define HISI_QM_API_VER3_BASE "hisi_qm_v3"
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/* UACCE_CMD_QM_SET_QP_CTX: Set qp algorithm type */
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#define UACCE_CMD_QM_SET_QP_CTX _IOWR('H', 10, struct hisi_qp_ctx)
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/* UACCE_CMD_QM_SET_QP_INFO: Set qp depth and BD size */
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#define UACCE_CMD_QM_SET_QP_INFO _IOWR('H', 11, struct hisi_qp_info)
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#endif
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