irqchip/irq-brcmstb-l2: Set IRQ_LEVEL for level triggered interrupts
[ Upstream commit94debe03e8
] When support for the level triggered interrupt controller flavor was added withc0ca726208
, we forgot to update the flags to be set to contain IRQ_LEVEL. While the flow handler is correct, the output from /proc/interrupts does not show such interrupts as being level triggered when they are, correct that. Fixes:c0ca726208
("irqchip/brcmstb-l2: Add support for the BCM7271 L2 controller") Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20221216230934.2478345-2-f.fainelli@gmail.com Signed-off-by: Sasha Levin <sashal@kernel.org>
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@ -161,6 +161,7 @@ static int __init brcmstb_l2_intc_of_init(struct device_node *np,
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*init_params)
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*init_params)
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{
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{
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unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
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unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
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unsigned int set = 0;
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struct brcmstb_l2_intc_data *data;
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struct brcmstb_l2_intc_data *data;
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struct irq_chip_type *ct;
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struct irq_chip_type *ct;
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int ret;
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int ret;
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@ -208,9 +209,12 @@ static int __init brcmstb_l2_intc_of_init(struct device_node *np,
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if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
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if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
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flags |= IRQ_GC_BE_IO;
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flags |= IRQ_GC_BE_IO;
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if (init_params->handler == handle_level_irq)
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set |= IRQ_LEVEL;
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/* Allocate a single Generic IRQ chip for this node */
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/* Allocate a single Generic IRQ chip for this node */
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ret = irq_alloc_domain_generic_chips(data->domain, 32, 1,
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ret = irq_alloc_domain_generic_chips(data->domain, 32, 1,
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np->full_name, init_params->handler, clr, 0, flags);
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np->full_name, init_params->handler, clr, set, flags);
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if (ret) {
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if (ret) {
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pr_err("failed to allocate generic irq chip\n");
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pr_err("failed to allocate generic irq chip\n");
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goto out_free_domain;
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goto out_free_domain;
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