bus: ti-sysc: Flush posted write only after srst_udelay
commit f71f6ff8c1f682a1cae4e8d7bdeed9d7f76b8f75 upstream. Commit34539b442b
("bus: ti-sysc: Flush posted write on enable before reset") caused a regression reproducable on omap4 duovero where the ISS target module can produce interconnect errors on boot. Turns out the registers are not accessible until after a delay for devices needing a ti,sysc-delay-us value. Let's fix this by flushing the posted write only after the reset delay. We do flushing also for ti,sysc-delay-us using devices as that should trigger an interconnect error if the delay is not properly configured. Let's also add some comments while at it. Fixes:34539b442b
("bus: ti-sysc: Flush posted write on enable before reset") Cc: stable@vger.kernel.org Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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@ -2174,13 +2174,23 @@ static int sysc_reset(struct sysc *ddata)
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sysc_val = sysc_read_sysconfig(ddata);
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sysc_val = sysc_read_sysconfig(ddata);
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sysc_val |= sysc_mask;
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sysc_val |= sysc_mask;
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sysc_write(ddata, sysc_offset, sysc_val);
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sysc_write(ddata, sysc_offset, sysc_val);
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/* Flush posted write */
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sysc_val = sysc_read_sysconfig(ddata);
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}
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/*
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* Some devices need a delay before reading registers
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* after reset. Presumably a srst_udelay is not needed
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* for devices that use a rstctrl register reset.
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*/
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if (ddata->cfg.srst_udelay)
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if (ddata->cfg.srst_udelay)
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fsleep(ddata->cfg.srst_udelay);
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fsleep(ddata->cfg.srst_udelay);
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/*
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* Flush posted write. For devices needing srst_udelay
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* this should trigger an interconnect error if the
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* srst_udelay value is needed but not configured.
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*/
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sysc_val = sysc_read_sysconfig(ddata);
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}
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if (ddata->post_reset_quirk)
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if (ddata->post_reset_quirk)
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ddata->post_reset_quirk(ddata);
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ddata->post_reset_quirk(ddata);
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