i2c: hisi: Only use the completion interrupt to finish the transfer
[ Upstream commitd982635126
] The controller will always generate a completion interrupt when the transfer is finished normally or not. Currently we use either error or completion interrupt to finish, this may result the completion interrupt unhandled and corrupt the next transfer, especially at low speed mode. Since on error case, the error interrupt will come first then is the completion interrupt. So only use the completion interrupt to finish the whole transfer process. Fixes:d62fbdb99a
("i2c: add support for HiSilicon I2C controller") Reported-by: Sheng Feng <fengsheng5@huawei.com> Signed-off-by: Sheng Feng <fengsheng5@huawei.com> Signed-off-by: Yicong Yang <yangyicong@hisilicon.com> Signed-off-by: Wolfram Sang <wsa@kernel.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
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@ -339,7 +339,11 @@ static irqreturn_t hisi_i2c_irq(int irq, void *context)
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hisi_i2c_read_rx_fifo(ctlr);
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hisi_i2c_read_rx_fifo(ctlr);
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out:
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out:
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if (int_stat & HISI_I2C_INT_TRANS_CPLT || ctlr->xfer_err) {
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/*
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* Only use TRANS_CPLT to indicate the completion. On error cases we'll
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* get two interrupts, INT_ERR first then TRANS_CPLT.
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*/
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if (int_stat & HISI_I2C_INT_TRANS_CPLT) {
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hisi_i2c_disable_int(ctlr, HISI_I2C_INT_ALL);
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hisi_i2c_disable_int(ctlr, HISI_I2C_INT_ALL);
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hisi_i2c_clear_int(ctlr, HISI_I2C_INT_ALL);
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hisi_i2c_clear_int(ctlr, HISI_I2C_INT_ALL);
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complete(ctlr->completion);
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complete(ctlr->completion);
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