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arm64: tegra: Add GPCDMA support for Tegra I2C 

Add dma properties to support GPCDMA for I2C in Tegra 186 and later
chips

Signed-off-by: Akhil R <akhilrajeev@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
This commit is contained in:
Akhil R 2022-09-06 20:17:15 +05:30 committed by Thierry Reding
parent af4c27738c
commit 8e4428051d
3 changed files with 96 additions and 0 deletions
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32
arch/arm64/boot/dts/nvidia/tegra186.dtsi
View File

@ -672,6 +672,10 @@ gen1_i2c: i2c@3160000 {
clock-names = "div-clk";
resets = <&bpmp TEGRA186_RESET_I2C1>;
reset-names = "i2c";
iommus = <&smmu TEGRA186_SID_GPCDMA_0>;
dma-coherent;
dmas = <&gpcdma 21>, <&gpcdma 21>;
dma-names = "rx", "tx";
status = "disabled";
};
@ -685,6 +689,10 @@ cam_i2c: i2c@3180000 {
clock-names = "div-clk";
resets = <&bpmp TEGRA186_RESET_I2C3>;
reset-names = "i2c";
iommus = <&smmu TEGRA186_SID_GPCDMA_0>;
dma-coherent;
dmas = <&gpcdma 23>, <&gpcdma 23>;
dma-names = "rx", "tx";
status = "disabled";
};
@ -702,6 +710,10 @@ dp_aux_ch1_i2c: i2c@3190000 {
pinctrl-names = "default", "idle";
pinctrl-0 = <&state_dpaux1_i2c>;
pinctrl-1 = <&state_dpaux1_off>;
iommus = <&smmu TEGRA186_SID_GPCDMA_0>;
dma-coherent;
dmas = <&gpcdma 26>, <&gpcdma 26>;
dma-names = "rx", "tx";
status = "disabled";
};
@ -733,6 +745,10 @@ dp_aux_ch0_i2c: i2c@31b0000 {
pinctrl-names = "default", "idle";
pinctrl-0 = <&state_dpaux_i2c>;
pinctrl-1 = <&state_dpaux_off>;
iommus = <&smmu TEGRA186_SID_GPCDMA_0>;
dma-coherent;
dmas = <&gpcdma 30>, <&gpcdma 30>;
dma-names = "rx", "tx";
status = "disabled";
};
@ -746,6 +762,10 @@ gen7_i2c: i2c@31c0000 {
clock-names = "div-clk";
resets = <&bpmp TEGRA186_RESET_I2C7>;
reset-names = "i2c";
iommus = <&smmu TEGRA186_SID_GPCDMA_0>;
dma-coherent;
dmas = <&gpcdma 27>, <&gpcdma 27>;
dma-names = "rx", "tx";
status = "disabled";
};
@ -759,6 +779,10 @@ gen9_i2c: i2c@31e0000 {
clock-names = "div-clk";
resets = <&bpmp TEGRA186_RESET_I2C9>;
reset-names = "i2c";
iommus = <&smmu TEGRA186_SID_GPCDMA_0>;
dma-coherent;
dmas = <&gpcdma 31>, <&gpcdma 31>;
dma-names = "rx", "tx";
status = "disabled";
};
@ -1176,6 +1200,10 @@ gen2_i2c: i2c@c240000 {
clock-names = "div-clk";
resets = <&bpmp TEGRA186_RESET_I2C2>;
reset-names = "i2c";
iommus = <&smmu TEGRA186_SID_GPCDMA_0>;
dma-coherent;
dmas = <&gpcdma 22>, <&gpcdma 22>;
dma-names = "rx", "tx";
status = "disabled";
};
@ -1189,6 +1217,10 @@ gen8_i2c: i2c@c250000 {
clock-names = "div-clk";
resets = <&bpmp TEGRA186_RESET_I2C8>;
reset-names = "i2c";
iommus = <&smmu TEGRA186_SID_GPCDMA_0>;
dma-coherent;
dmas = <&gpcdma 0>, <&gpcdma 0>;
dma-names = "rx", "tx";
status = "disabled";
};

32
arch/arm64/boot/dts/nvidia/tegra194.dtsi
View File

@ -805,6 +805,10 @@ gen1_i2c: i2c@3160000 {
clock-names = "div-clk";
resets = <&bpmp TEGRA194_RESET_I2C1>;
reset-names = "i2c";
iommus = <&smmu TEGRA194_SID_GPCDMA_0>;
dma-coherent;
dmas = <&gpcdma 21>, <&gpcdma 21>;
dma-names = "rx", "tx";
status = "disabled";
};
@ -830,6 +834,10 @@ cam_i2c: i2c@3180000 {
clock-names = "div-clk";
resets = <&bpmp TEGRA194_RESET_I2C3>;
reset-names = "i2c";
iommus = <&smmu TEGRA194_SID_GPCDMA_0>;
dma-coherent;
dmas = <&gpcdma 23>, <&gpcdma 23>;
dma-names = "rx", "tx";
status = "disabled";
};
@ -847,6 +855,10 @@ dp_aux_ch1_i2c: i2c@3190000 {
pinctrl-0 = <&state_dpaux1_i2c>;
pinctrl-1 = <&state_dpaux1_off>;
pinctrl-names = "default", "idle";
iommus = <&smmu TEGRA194_SID_GPCDMA_0>;
dma-coherent;
dmas = <&gpcdma 26>, <&gpcdma 26>;
dma-names = "rx", "tx";
status = "disabled";
};
@ -864,6 +876,10 @@ dp_aux_ch0_i2c: i2c@31b0000 {
pinctrl-0 = <&state_dpaux0_i2c>;
pinctrl-1 = <&state_dpaux0_off>;
pinctrl-names = "default", "idle";
iommus = <&smmu TEGRA194_SID_GPCDMA_0>;
dma-coherent;
dmas = <&gpcdma 30>, <&gpcdma 30>;
dma-names = "rx", "tx";
status = "disabled";
};
@ -881,6 +897,10 @@ dp_aux_ch2_i2c: i2c@31c0000 {
pinctrl-0 = <&state_dpaux2_i2c>;
pinctrl-1 = <&state_dpaux2_off>;
pinctrl-names = "default", "idle";
iommus = <&smmu TEGRA194_SID_GPCDMA_0>;
dma-coherent;
dmas = <&gpcdma 27>, <&gpcdma 27>;
dma-names = "rx", "tx";
status = "disabled";
};
@ -898,6 +918,10 @@ dp_aux_ch3_i2c: i2c@31e0000 {
pinctrl-0 = <&state_dpaux3_i2c>;
pinctrl-1 = <&state_dpaux3_off>;
pinctrl-names = "default", "idle";
iommus = <&smmu TEGRA194_SID_GPCDMA_0>;
dma-coherent;
dmas = <&gpcdma 31>, <&gpcdma 31>;
dma-names = "rx", "tx";
status = "disabled";
};
@ -1565,6 +1589,10 @@ gen2_i2c: i2c@c240000 {
clock-names = "div-clk";
resets = <&bpmp TEGRA194_RESET_I2C2>;
reset-names = "i2c";
iommus = <&smmu TEGRA194_SID_GPCDMA_0>;
dma-coherent;
dmas = <&gpcdma 22>, <&gpcdma 22>;
dma-names = "rx", "tx";
status = "disabled";
};
@ -1578,6 +1606,10 @@ gen8_i2c: i2c@c250000 {
clock-names = "div-clk";
resets = <&bpmp TEGRA194_RESET_I2C8>;
reset-names = "i2c";
iommus = <&smmu TEGRA194_SID_GPCDMA_0>;
dma-coherent;
dmas = <&gpcdma 0>, <&gpcdma 0>;
dma-names = "rx", "tx";
status = "disabled";
};

32
arch/arm64/boot/dts/nvidia/tegra234.dtsi
View File

@ -754,6 +754,10 @@ gen1_i2c: i2c@3160000 {
clock-names = "div-clk", "parent";
resets = <&bpmp TEGRA234_RESET_I2C1>;
reset-names = "i2c";
iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>;
dma-coherent;
dmas = <&gpcdma 21>, <&gpcdma 21>;
dma-names = "rx", "tx";
};
cam_i2c: i2c@3180000 {
@ -769,6 +773,10 @@ cam_i2c: i2c@3180000 {
clock-names = "div-clk", "parent";
resets = <&bpmp TEGRA234_RESET_I2C3>;
reset-names = "i2c";
iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>;
dma-coherent;
dmas = <&gpcdma 23>, <&gpcdma 23>;
dma-names = "rx", "tx";
};
dp_aux_ch1_i2c: i2c@3190000 {
@ -784,6 +792,10 @@ dp_aux_ch1_i2c: i2c@3190000 {
clock-names = "div-clk", "parent";
resets = <&bpmp TEGRA234_RESET_I2C4>;
reset-names = "i2c";
iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>;
dma-coherent;
dmas = <&gpcdma 26>, <&gpcdma 26>;
dma-names = "rx", "tx";
};
dp_aux_ch0_i2c: i2c@31b0000 {
@ -799,6 +811,10 @@ dp_aux_ch0_i2c: i2c@31b0000 {
clock-names = "div-clk", "parent";
resets = <&bpmp TEGRA234_RESET_I2C6>;
reset-names = "i2c";
iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>;
dma-coherent;
dmas = <&gpcdma 30>, <&gpcdma 30>;
dma-names = "rx", "tx";
};
dp_aux_ch2_i2c: i2c@31c0000 {
@ -814,6 +830,10 @@ dp_aux_ch2_i2c: i2c@31c0000 {
clock-names = "div-clk", "parent";
resets = <&bpmp TEGRA234_RESET_I2C7>;
reset-names = "i2c";
iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>;
dma-coherent;
dmas = <&gpcdma 27>, <&gpcdma 27>;
dma-names = "rx", "tx";
};
dp_aux_ch3_i2c: i2c@31e0000 {
@ -829,6 +849,10 @@ dp_aux_ch3_i2c: i2c@31e0000 {
clock-names = "div-clk", "parent";
resets = <&bpmp TEGRA234_RESET_I2C9>;
reset-names = "i2c";
iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>;
dma-coherent;
dmas = <&gpcdma 31>, <&gpcdma 31>;
dma-names = "rx", "tx";
};
spi@3270000 {
@ -1455,6 +1479,10 @@ gen2_i2c: i2c@c240000 {
assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
resets = <&bpmp TEGRA234_RESET_I2C2>;
reset-names = "i2c";
iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>;
dma-coherent;
dmas = <&gpcdma 22>, <&gpcdma 22>;
dma-names = "rx", "tx";
};
gen8_i2c: i2c@c250000 {
@ -1471,6 +1499,10 @@ gen8_i2c: i2c@c250000 {
assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
resets = <&bpmp TEGRA234_RESET_I2C8>;
reset-names = "i2c";
iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>;
dma-coherent;
dmas = <&gpcdma 0>, <&gpcdma 0>;
dma-names = "rx", "tx";
};
rtc@c2a0000 {