ARC: mm: support 4 levels of page tables
Acked-by: Mike Rapoport <rppt@linux.ibm.com> Signed-off-by: Vineet Gupta <vgupta@kernel.org>
This commit is contained in:
Vineet Gupta
parent
2dde02ab6d
commit
8747ff704a
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@ -41,6 +41,17 @@ typedef struct {
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#define pgd_val(x) ((x).pgd)
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#define __pgd(x) ((pgd_t) { (x) })
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#if CONFIG_PGTABLE_LEVELS > 3
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typedef struct {
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unsigned long pud;
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} pud_t;
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#define pud_val(x) ((x).pud)
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#define __pud(x) ((pud_t) { (x) })
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#endif
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#if CONFIG_PGTABLE_LEVELS > 2
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typedef struct {
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@ -70,6 +70,17 @@ static inline pgd_t *pgd_alloc(struct mm_struct *mm)
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return ret;
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}
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#if CONFIG_PGTABLE_LEVELS > 3
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static inline void p4d_populate(struct mm_struct *mm, p4d_t *p4dp, pud_t *pudp)
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{
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set_p4d(p4dp, __p4d((unsigned long)pudp));
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}
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#define __pud_free_tlb(tlb, pmd, addr) pud_free((tlb)->mm, pmd)
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#endif
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#if CONFIG_PGTABLE_LEVELS > 2
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static inline void pud_populate(struct mm_struct *mm, pud_t *pudp, pmd_t *pmdp)
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@ -54,8 +54,13 @@
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/*
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* A default 3 level paging testing setup in software walked MMU
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* MMUv4 (8K page): <4> : <7> : <8> : <13>
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* A default 4 level paging testing setup in software walked MMU
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* MMUv4 (8K page): <4> : <3> : <4> : <8> : <13>
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*/
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#define PGDIR_SHIFT 28
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#if CONFIG_PGTABLE_LEVELS > 3
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#define PUD_SHIFT 25
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#endif
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#if CONFIG_PGTABLE_LEVELS > 2
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#define PMD_SHIFT 21
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#endif
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@ -66,17 +71,25 @@
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#define PGDIR_MASK (~(PGDIR_SIZE - 1))
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#define PTRS_PER_PGD BIT(32 - PGDIR_SHIFT)
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#if CONFIG_PGTABLE_LEVELS > 3
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#define PUD_SIZE BIT(PUD_SHIFT)
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#define PUD_MASK (~(PUD_SIZE - 1))
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#define PTRS_PER_PUD BIT(PGDIR_SHIFT - PUD_SHIFT)
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#endif
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#if CONFIG_PGTABLE_LEVELS > 2
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#define PMD_SIZE BIT(PMD_SHIFT)
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#define PMD_MASK (~(PMD_SIZE - 1))
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#define PTRS_PER_PMD BIT(PGDIR_SHIFT - PMD_SHIFT)
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#define PTRS_PER_PMD BIT(PUD_SHIFT - PMD_SHIFT)
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#endif
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#define PTRS_PER_PTE BIT(PMD_SHIFT - PAGE_SHIFT)
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#ifndef __ASSEMBLY__
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#if CONFIG_PGTABLE_LEVELS > 2
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#if CONFIG_PGTABLE_LEVELS > 3
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#include <asm-generic/pgtable-nop4d.h>
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#elif CONFIG_PGTABLE_LEVELS > 2
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#include <asm-generic/pgtable-nopud.h>
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#else
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#include <asm-generic/pgtable-nopmd.h>
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@ -91,9 +104,31 @@
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#define pgd_ERROR(e) \
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pr_crit("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
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#if CONFIG_PGTABLE_LEVELS > 3
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/* In 4 level paging, p4d_* macros work on pgd */
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#define p4d_none(x) (!p4d_val(x))
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#define p4d_bad(x) ((p4d_val(x) & ~PAGE_MASK))
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#define p4d_present(x) (p4d_val(x))
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#define p4d_clear(xp) do { p4d_val(*(xp)) = 0; } while (0)
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#define p4d_pgtable(p4d) ((pud_t *)(p4d_val(p4d) & PAGE_MASK))
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#define p4d_page(p4d) virt_to_page(p4d_pgtable(p4d))
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#define set_p4d(p4dp, p4d) (*(p4dp) = p4d)
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/*
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* 2nd level paging: pud
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*/
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#define pud_ERROR(e) \
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pr_crit("%s:%d: bad pud %08lx.\n", __FILE__, __LINE__, pud_val(e))
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#endif
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#if CONFIG_PGTABLE_LEVELS > 2
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/* In 3 level paging, pud_* macros work on pgd */
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/*
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* In 3 level paging, pud_* macros work on pgd
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* In 4 level paging, pud_* macros work on pud
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*/
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#define pud_none(x) (!pud_val(x))
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#define pud_bad(x) ((pud_val(x) & ~PAGE_MASK))
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#define pud_present(x) (pud_val(x))
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@ -103,7 +138,7 @@
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#define set_pud(pudp, pud) (*(pudp) = pud)
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/*
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* 2nd level paging: pmd
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* 3rd level paging: pmd
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*/
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#define pmd_ERROR(e) \
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pr_crit("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e))
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@ -131,7 +166,7 @@
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#define pmd_pgtable(pmd) ((pgtable_t) pmd_page_vaddr(pmd))
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/*
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* 3rd level paging: pte
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* 4th level paging: pte
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*/
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#define pte_ERROR(e) \
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pr_crit("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
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@ -46,6 +46,8 @@ noinline static int handle_kernel_vaddr_fault(unsigned long address)
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if (!p4d_present(*p4d_k))
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goto bad_area;
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set_p4d(p4d, *p4d_k);
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pud = pud_offset(p4d, address);
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pud_k = pud_offset(p4d_k, address);
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if (!pud_present(*pud_k))
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@ -191,6 +191,7 @@ void __init mem_init(void)
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highmem_init();
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BUILD_BUG_ON((PTRS_PER_PGD * sizeof(pgd_t)) > PAGE_SIZE);
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BUILD_BUG_ON((PTRS_PER_PUD * sizeof(pud_t)) > PAGE_SIZE);
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BUILD_BUG_ON((PTRS_PER_PMD * sizeof(pmd_t)) > PAGE_SIZE);
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BUILD_BUG_ON((PTRS_PER_PTE * sizeof(pte_t)) > PAGE_SIZE);
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}
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@ -173,6 +173,15 @@ ex_saved_reg1:
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tst r3, r3
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bz do_slow_path_pf ; if no Page Table, do page fault
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#if CONFIG_PGTABLE_LEVELS > 3
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lsr r0, r2, PUD_SHIFT ; Bits for indexing into PUD
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and r0, r0, (PTRS_PER_PUD - 1)
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ld.as r1, [r3, r0] ; PMD entry
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tst r1, r1
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bz do_slow_path_pf
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mov r3, r1
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#endif
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#if CONFIG_PGTABLE_LEVELS > 2
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lsr r0, r2, PMD_SHIFT ; Bits for indexing into PMD
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and r0, r0, (PTRS_PER_PMD - 1)
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