mfd: intel-m10-bmc: Add PMCI driver
Add the mfd driver for the Platform Management Component Interface (PMCI) based interface of Intel MAX10 BMC controller. PMCI is a software-visible interface, connected to card BMC which provided the basic functionality of read/write BMC register. The access to the register is done indirectly via a hardware controller/bridge that handles read/write/clear commands and acknowledgments for the commands. Previously, intel-m10-bmc provided sysfs under /sys/bus/spi/devices/... which is generalized in this change because not all MAX10 BMC appear under SPI anymore. Co-developed-by: Tianfei zhang <tianfei.zhang@intel.com> Signed-off-by: Tianfei zhang <tianfei.zhang@intel.com> Co-developed-by: Russ Weight <russell.h.weight@intel.com> Signed-off-by: Russ Weight <russell.h.weight@intel.com> Co-developed-by: Matthew Gerlach <matthew.gerlach@linux.intel.com> Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com> Reviewed-by: Xu Yilun <yilun.xu@intel.com> Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> Signed-off-by: Lee Jones <lee@kernel.org> Link: https://lore.kernel.org/r/20230116100845.6153-11-ilpo.jarvinen@linux.intel.com
This commit is contained in:
Ilpo Järvinen
Lee Jones
parent
001a734a55
commit
869b9eddf0
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@ -1,4 +1,4 @@
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What: /sys/bus/spi/devices/.../bmc_version
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What: /sys/bus/.../drivers/intel-m10-bmc/.../bmc_version
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Date: June 2020
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KernelVersion: 5.10
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Contact: Xu Yilun <yilun.xu@intel.com>
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@ -6,7 +6,7 @@ Description: Read only. Returns the hardware build version of Intel
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MAX10 BMC chip.
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Format: "0x%x".
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What: /sys/bus/spi/devices/.../bmcfw_version
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What: /sys/bus/.../drivers/intel-m10-bmc/.../bmcfw_version
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Date: June 2020
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KernelVersion: 5.10
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Contact: Xu Yilun <yilun.xu@intel.com>
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@ -14,7 +14,7 @@ Description: Read only. Returns the firmware version of Intel MAX10
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BMC chip.
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Format: "0x%x".
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What: /sys/bus/spi/devices/.../mac_address
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What: /sys/bus/.../drivers/intel-m10-bmc/.../mac_address
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Date: January 2021
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KernelVersion: 5.12
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Contact: Russ Weight <russell.h.weight@intel.com>
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@ -25,7 +25,7 @@ Description: Read only. Returns the first MAC address in a block
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space.
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Format: "%02x:%02x:%02x:%02x:%02x:%02x".
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What: /sys/bus/spi/devices/.../mac_count
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What: /sys/bus/.../drivers/intel-m10-bmc/.../mac_count
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Date: January 2021
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KernelVersion: 5.12
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Contact: Russ Weight <russell.h.weight@intel.com>
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@ -2243,6 +2243,18 @@ config MFD_INTEL_M10_BMC_SPI
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additional drivers must be enabled in order to use the functionality
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of the device.
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config MFD_INTEL_M10_BMC_PMCI
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tristate "Intel MAX 10 Board Management Controller with PMCI"
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depends on FPGA_DFL
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select MFD_INTEL_M10_BMC_CORE
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select REGMAP
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help
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Support for the Intel MAX 10 board management controller via PMCI.
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This driver provides common support for accessing the device,
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additional drivers must be enabled in order to use the functionality
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of the device.
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config MFD_RSMU_I2C
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tristate "Renesas Synchronization Management Unit with I2C"
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depends on I2C && OF
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@ -272,6 +272,7 @@ obj-$(CONFIG_MFD_SMPRO) += smpro-core.o
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obj-$(CONFIG_MFD_INTEL_M10_BMC_CORE) += intel-m10-bmc-core.o
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obj-$(CONFIG_MFD_INTEL_M10_BMC_SPI) += intel-m10-bmc-spi.o
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obj-$(CONFIG_MFD_INTEL_M10_BMC_PMCI) += intel-m10-bmc-pmci.o
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obj-$(CONFIG_MFD_ATC260X) += atc260x-core.o
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obj-$(CONFIG_MFD_ATC260X_I2C) += atc260x-i2c.o
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@ -0,0 +1,219 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* MAX10 BMC Platform Management Component Interface (PMCI) based
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* interface.
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*
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* Copyright (C) 2020-2023 Intel Corporation.
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*/
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#include <linux/device.h>
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#include <linux/dfl.h>
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#include <linux/mfd/core.h>
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#include <linux/mfd/intel-m10-bmc.h>
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#include <linux/module.h>
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#include <linux/regmap.h>
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struct m10bmc_pmci_device {
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void __iomem *base;
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struct intel_m10bmc m10bmc;
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};
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/*
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* Intel FGPA indirect register access via hardware controller/bridge.
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*/
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#define INDIRECT_CMD_OFF 0
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#define INDIRECT_CMD_CLR 0
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#define INDIRECT_CMD_RD BIT(0)
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#define INDIRECT_CMD_WR BIT(1)
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#define INDIRECT_CMD_ACK BIT(2)
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#define INDIRECT_ADDR_OFF 0x4
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#define INDIRECT_RD_OFF 0x8
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#define INDIRECT_WR_OFF 0xc
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#define INDIRECT_INT_US 1
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#define INDIRECT_TIMEOUT_US 10000
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struct indirect_ctx {
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void __iomem *base;
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struct device *dev;
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};
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static int indirect_clear_cmd(struct indirect_ctx *ctx)
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{
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unsigned int cmd;
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int ret;
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writel(INDIRECT_CMD_CLR, ctx->base + INDIRECT_CMD_OFF);
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ret = readl_poll_timeout(ctx->base + INDIRECT_CMD_OFF, cmd,
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cmd == INDIRECT_CMD_CLR,
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INDIRECT_INT_US, INDIRECT_TIMEOUT_US);
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if (ret)
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dev_err(ctx->dev, "timed out waiting clear cmd (residual cmd=0x%x)\n", cmd);
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return ret;
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}
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static int indirect_reg_read(void *context, unsigned int reg, unsigned int *val)
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{
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struct indirect_ctx *ctx = context;
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unsigned int cmd, ack, tmpval;
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int ret, ret2;
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cmd = readl(ctx->base + INDIRECT_CMD_OFF);
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if (cmd != INDIRECT_CMD_CLR)
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dev_warn(ctx->dev, "residual cmd 0x%x on read entry\n", cmd);
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writel(reg, ctx->base + INDIRECT_ADDR_OFF);
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writel(INDIRECT_CMD_RD, ctx->base + INDIRECT_CMD_OFF);
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ret = readl_poll_timeout(ctx->base + INDIRECT_CMD_OFF, ack,
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(ack & INDIRECT_CMD_ACK) == INDIRECT_CMD_ACK,
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INDIRECT_INT_US, INDIRECT_TIMEOUT_US);
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if (ret)
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dev_err(ctx->dev, "read timed out on reg 0x%x ack 0x%x\n", reg, ack);
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else
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tmpval = readl(ctx->base + INDIRECT_RD_OFF);
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ret2 = indirect_clear_cmd(ctx);
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if (ret)
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return ret;
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if (ret2)
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return ret2;
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*val = tmpval;
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return 0;
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}
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static int indirect_reg_write(void *context, unsigned int reg, unsigned int val)
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{
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struct indirect_ctx *ctx = context;
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unsigned int cmd, ack;
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int ret, ret2;
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cmd = readl(ctx->base + INDIRECT_CMD_OFF);
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if (cmd != INDIRECT_CMD_CLR)
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dev_warn(ctx->dev, "residual cmd 0x%x on write entry\n", cmd);
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writel(val, ctx->base + INDIRECT_WR_OFF);
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writel(reg, ctx->base + INDIRECT_ADDR_OFF);
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writel(INDIRECT_CMD_WR, ctx->base + INDIRECT_CMD_OFF);
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ret = readl_poll_timeout(ctx->base + INDIRECT_CMD_OFF, ack,
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(ack & INDIRECT_CMD_ACK) == INDIRECT_CMD_ACK,
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INDIRECT_INT_US, INDIRECT_TIMEOUT_US);
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if (ret)
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dev_err(ctx->dev, "write timed out on reg 0x%x ack 0x%x\n", reg, ack);
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ret2 = indirect_clear_cmd(ctx);
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if (ret)
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return ret;
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return ret2;
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}
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static const struct regmap_range m10bmc_pmci_regmap_range[] = {
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regmap_reg_range(M10BMC_N6000_SYS_BASE, M10BMC_N6000_SYS_END),
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};
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static const struct regmap_access_table m10bmc_pmci_access_table = {
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.yes_ranges = m10bmc_pmci_regmap_range,
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.n_yes_ranges = ARRAY_SIZE(m10bmc_pmci_regmap_range),
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};
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static struct regmap_config m10bmc_pmci_regmap_config = {
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.reg_bits = 32,
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.reg_stride = 4,
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.val_bits = 32,
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.wr_table = &m10bmc_pmci_access_table,
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.rd_table = &m10bmc_pmci_access_table,
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.reg_read = &indirect_reg_read,
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.reg_write = &indirect_reg_write,
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.max_register = M10BMC_N6000_SYS_END,
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};
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static struct mfd_cell m10bmc_pmci_n6000_bmc_subdevs[] = {
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{ .name = "n6000bmc-hwmon" },
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};
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static const struct m10bmc_csr_map m10bmc_n6000_csr_map = {
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.base = M10BMC_N6000_SYS_BASE,
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.build_version = M10BMC_N6000_BUILD_VER,
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.fw_version = NIOS2_N6000_FW_VERSION,
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.mac_low = M10BMC_N6000_MAC_LOW,
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.mac_high = M10BMC_N6000_MAC_HIGH,
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.doorbell = M10BMC_N6000_DOORBELL,
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.auth_result = M10BMC_N6000_AUTH_RESULT,
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.bmc_prog_addr = M10BMC_N6000_BMC_PROG_ADDR,
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.bmc_reh_addr = M10BMC_N6000_BMC_REH_ADDR,
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.bmc_magic = M10BMC_N6000_BMC_PROG_MAGIC,
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.sr_prog_addr = M10BMC_N6000_SR_PROG_ADDR,
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.sr_reh_addr = M10BMC_N6000_SR_REH_ADDR,
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.sr_magic = M10BMC_N6000_SR_PROG_MAGIC,
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.pr_prog_addr = M10BMC_N6000_PR_PROG_ADDR,
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.pr_reh_addr = M10BMC_N6000_PR_REH_ADDR,
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.pr_magic = M10BMC_N6000_PR_PROG_MAGIC,
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.rsu_update_counter = M10BMC_N6000_STAGING_FLASH_COUNT,
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};
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static const struct intel_m10bmc_platform_info m10bmc_pmci_n6000 = {
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.cells = m10bmc_pmci_n6000_bmc_subdevs,
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.n_cells = ARRAY_SIZE(m10bmc_pmci_n6000_bmc_subdevs),
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.csr_map = &m10bmc_n6000_csr_map,
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};
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static int m10bmc_pmci_probe(struct dfl_device *ddev)
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{
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struct device *dev = &ddev->dev;
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struct m10bmc_pmci_device *pmci;
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struct indirect_ctx *ctx;
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pmci = devm_kzalloc(dev, sizeof(*pmci), GFP_KERNEL);
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if (!pmci)
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return -ENOMEM;
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pmci->m10bmc.dev = dev;
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pmci->base = devm_ioremap_resource(dev, &ddev->mmio_res);
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if (IS_ERR(pmci->base))
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return PTR_ERR(pmci->base);
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ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
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if (!ctx)
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return -ENOMEM;
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ctx->base = pmci->base + M10BMC_N6000_INDIRECT_BASE;
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ctx->dev = dev;
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indirect_clear_cmd(ctx);
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pmci->m10bmc.regmap = devm_regmap_init(dev, NULL, ctx, &m10bmc_pmci_regmap_config);
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if (IS_ERR(pmci->m10bmc.regmap))
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return PTR_ERR(pmci->m10bmc.regmap);
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return m10bmc_dev_init(&pmci->m10bmc, &m10bmc_pmci_n6000);
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}
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#define FME_FEATURE_ID_M10BMC_PMCI 0x12
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static const struct dfl_device_id m10bmc_pmci_ids[] = {
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{ FME_ID, FME_FEATURE_ID_M10BMC_PMCI },
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{ }
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};
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MODULE_DEVICE_TABLE(dfl, m10bmc_pmci_ids);
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static struct dfl_driver m10bmc_pmci_driver = {
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.drv = {
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.name = "intel-m10-bmc",
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.dev_groups = m10bmc_dev_groups,
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},
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.id_table = m10bmc_pmci_ids,
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.probe = m10bmc_pmci_probe,
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};
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module_dfl_driver(m10bmc_pmci_driver);
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MODULE_DESCRIPTION("MAX10 BMC PMCI-based interface");
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MODULE_AUTHOR("Intel Corporation");
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MODULE_LICENSE("GPL");
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@ -120,6 +120,34 @@
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/* Address of 4KB inverted bit vector containing staging area FLASH count */
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#define M10BMC_N3000_STAGING_FLASH_COUNT 0x17ffb000
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#define M10BMC_N6000_INDIRECT_BASE 0x400
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#define M10BMC_N6000_SYS_BASE 0x0
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#define M10BMC_N6000_SYS_END 0xfff
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#define M10BMC_N6000_DOORBELL 0x1c0
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#define M10BMC_N6000_AUTH_RESULT 0x1c4
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#define M10BMC_N6000_BUILD_VER 0x0
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#define NIOS2_N6000_FW_VERSION 0x4
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#define M10BMC_N6000_MAC_LOW 0x20
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#define M10BMC_N6000_MAC_HIGH (M10BMC_N6000_MAC_LOW + 4)
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/* Addresses for security related data in FLASH */
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#define M10BMC_N6000_BMC_REH_ADDR 0x7ffc004
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#define M10BMC_N6000_BMC_PROG_ADDR 0x7ffc000
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#define M10BMC_N6000_BMC_PROG_MAGIC 0x5746
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#define M10BMC_N6000_SR_REH_ADDR 0x7ffd004
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#define M10BMC_N6000_SR_PROG_ADDR 0x7ffd000
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#define M10BMC_N6000_SR_PROG_MAGIC 0x5253
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#define M10BMC_N6000_PR_REH_ADDR 0x7ffe004
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#define M10BMC_N6000_PR_PROG_ADDR 0x7ffe000
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#define M10BMC_N6000_PR_PROG_MAGIC 0x5250
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#define M10BMC_N6000_STAGING_FLASH_COUNT 0x7ff5000
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/**
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* struct m10bmc_csr_map - Intel MAX 10 BMC CSR register map
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*/
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