memory: renesas-rpc-if: Fix HF/OSPI data transfer in Manual Mode
HyperFlash devices fail to probe:
rpc-if-hyperflash rpc-if-hyperflash: probing of hyperbus device failed
In HyperFlash or Octal-SPI Flash mode, the Transfer Data Enable bits
(SPIDE) in the Manual Mode Enable Setting Register (SMENR) are derived
from half of the transfer size, cfr. the rpcif_bits_set() helper
function. However, rpcif_reg_{read,write}() does not take the bus size
into account, and does not double all Manual Mode Data Register access
sizes when communicating with a HyperFlash or Octal-SPI Flash device.
Fix this, and avoid the back-and-forth conversion between transfer size
and Transfer Data Enable bits, by explicitly storing the transfer size
in struct rpcif, and using that value to determine access size in
rpcif_reg_{read,write}().
Enforce that the "high" Manual Mode Read/Write Data Registers
(SM[RW]DR1) are only used for 8-byte data accesses.
While at it, forbid writing to the Manual Mode Read Data Registers,
as they are read-only.
Fixes: fff53a551d
("memory: renesas-rpc-if: Correct QSPI data transfer in Manual mode")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Tested-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/cde9bfacf704c81865f57b15d1b48a4793da4286.1649681476.git.geert+renesas@glider.be
Link: https://lore.kernel.org/r/20220420070526.9367-1-krzysztof.kozlowski@linaro.org'
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
parent
67e473a303
commit
7e842d70fe
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@ -164,25 +164,39 @@ static const struct regmap_access_table rpcif_volatile_table = {
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/*
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* Custom accessor functions to ensure SMRDR0 and SMWDR0 are always accessed
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* with proper width. Requires SMENR_SPIDE to be correctly set before!
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* Custom accessor functions to ensure SM[RW]DR[01] are always accessed with
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* proper width. Requires rpcif.xfer_size to be correctly set before!
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*/
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static int rpcif_reg_read(void *context, unsigned int reg, unsigned int *val)
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{
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struct rpcif *rpc = context;
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if (reg == RPCIF_SMRDR0 || reg == RPCIF_SMWDR0) {
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u32 spide = readl(rpc->base + RPCIF_SMENR) & RPCIF_SMENR_SPIDE(0xF);
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if (spide == 0x8) {
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switch (reg) {
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case RPCIF_SMRDR0:
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case RPCIF_SMWDR0:
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switch (rpc->xfer_size) {
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case 1:
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*val = readb(rpc->base + reg);
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return 0;
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} else if (spide == 0xC) {
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case 2:
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*val = readw(rpc->base + reg);
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return 0;
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} else if (spide != 0xF) {
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case 4:
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case 8:
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*val = readl(rpc->base + reg);
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return 0;
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default:
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return -EILSEQ;
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}
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case RPCIF_SMRDR1:
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case RPCIF_SMWDR1:
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if (rpc->xfer_size != 8)
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return -EILSEQ;
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break;
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}
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*val = readl(rpc->base + reg);
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@ -193,18 +207,34 @@ static int rpcif_reg_write(void *context, unsigned int reg, unsigned int val)
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{
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struct rpcif *rpc = context;
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if (reg == RPCIF_SMRDR0 || reg == RPCIF_SMWDR0) {
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u32 spide = readl(rpc->base + RPCIF_SMENR) & RPCIF_SMENR_SPIDE(0xF);
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if (spide == 0x8) {
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switch (reg) {
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case RPCIF_SMWDR0:
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switch (rpc->xfer_size) {
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case 1:
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writeb(val, rpc->base + reg);
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return 0;
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} else if (spide == 0xC) {
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case 2:
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writew(val, rpc->base + reg);
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return 0;
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} else if (spide != 0xF) {
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case 4:
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case 8:
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writel(val, rpc->base + reg);
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return 0;
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default:
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return -EILSEQ;
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}
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case RPCIF_SMWDR1:
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if (rpc->xfer_size != 8)
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return -EILSEQ;
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break;
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case RPCIF_SMRDR0:
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case RPCIF_SMRDR1:
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return -EPERM;
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}
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writel(val, rpc->base + reg);
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@ -469,6 +499,7 @@ int rpcif_manual_xfer(struct rpcif *rpc)
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smenr |= RPCIF_SMENR_SPIDE(rpcif_bits_set(rpc, nbytes));
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regmap_write(rpc->regmap, RPCIF_SMENR, smenr);
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rpc->xfer_size = nbytes;
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memcpy(data, rpc->buffer + pos, nbytes);
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if (nbytes == 8) {
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@ -533,6 +564,7 @@ int rpcif_manual_xfer(struct rpcif *rpc)
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regmap_write(rpc->regmap, RPCIF_SMENR, smenr);
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regmap_write(rpc->regmap, RPCIF_SMCR,
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rpc->smcr | RPCIF_SMCR_SPIE);
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rpc->xfer_size = nbytes;
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ret = wait_msg_xfer_end(rpc);
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if (ret)
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goto err_out;
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@ -72,6 +72,7 @@ struct rpcif {
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enum rpcif_type type;
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enum rpcif_data_dir dir;
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u8 bus_size;
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u8 xfer_size;
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void *buffer;
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u32 xferlen;
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u32 smcr;
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