OrgACRN
/
acrn-kernel
mirror of https://github.com/projectacrn/acrn-kernel.git
1
0
Fork 0
Code Issues Releases Wiki Activity

ASoC: Intel: avs: Power and clock gating policy overriding 

commit 2a87f17775 upstream.

Provide pgctl/cgctl_mask module parameters for overriding power and
clock gating policies respectively. These help deal with rare firmware
loading failures on some configurations. There're no golden masks that
cover all known problems so leave the defaults as is.

While at it, update avs_hda_l1sen_enable()'s definition so it aligns
with its power/clock friends.

Signed-off-by: Cezary Rojewski <cezary.rojewski@intel.com>
Link: https://lore.kernel.org/r/20221027124702.1761002-9-cezary.rojewski@intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Cezary Rojewski 2022-10-27 14:47:01 +02:00
parent bffa954953
commit 7b67eb0f70
1 changed files with 13 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

22
sound/soc/intel/avs/core.c
View File

@ -27,6 +27,14 @@
#include "avs.h" #include "avs.h"
#include "cldma.h" #include "cldma.h"
static u32 pgctl_mask = AZX_PGCTL_LSRMD_MASK;
module_param(pgctl_mask, uint, 0444);
MODULE_PARM_DESC(pgctl_mask, "PCI PGCTL policy override");
static u32 cgctl_mask = AZX_CGCTL_MISCBDCGE_MASK;
module_param(cgctl_mask, uint, 0444);
MODULE_PARM_DESC(cgctl_mask, "PCI CGCTL policy override");
static void static void
avs_hda_update_config_dword(struct hdac_bus *bus, u32 reg, u32 mask, u32 value) avs_hda_update_config_dword(struct hdac_bus *bus, u32 reg, u32 mask, u32 value)
{ {
@ -41,19 +49,16 @@ avs_hda_update_config_dword(struct hdac_bus *bus, u32 reg, u32 mask, u32 value)
void avs_hda_power_gating_enable(struct avs_dev *adev, bool enable) void avs_hda_power_gating_enable(struct avs_dev *adev, bool enable)
{ {
u32 value; u32 value = enable ? 0 : pgctl_mask;
value = enable ? 0 : AZX_PGCTL_LSRMD_MASK; avs_hda_update_config_dword(&adev->base.core, AZX_PCIREG_PGCTL, pgctl_mask, value);
avs_hda_update_config_dword(&adev->base.core, AZX_PCIREG_PGCTL,
AZX_PGCTL_LSRMD_MASK, value);
} }
static void avs_hdac_clock_gating_enable(struct hdac_bus *bus, bool enable) static void avs_hdac_clock_gating_enable(struct hdac_bus *bus, bool enable)
{ {
u32 value; u32 value = enable ? cgctl_mask : 0;
value = enable ? AZX_CGCTL_MISCBDCGE_MASK : 0; avs_hda_update_config_dword(bus, AZX_PCIREG_CGCTL, cgctl_mask, value);
avs_hda_update_config_dword(bus, AZX_PCIREG_CGCTL, AZX_CGCTL_MISCBDCGE_MASK, value);
} }
void avs_hda_clock_gating_enable(struct avs_dev *adev, bool enable) void avs_hda_clock_gating_enable(struct avs_dev *adev, bool enable)
@ -63,9 +68,8 @@ void avs_hda_clock_gating_enable(struct avs_dev *adev, bool enable)
void avs_hda_l1sen_enable(struct avs_dev *adev, bool enable) void avs_hda_l1sen_enable(struct avs_dev *adev, bool enable)
{ {
u32 value; u32 value = enable ? AZX_VS_EM2_L1SEN : 0;
value = enable ? AZX_VS_EM2_L1SEN : 0;
snd_hdac_chip_updatel(&adev->base.core, VS_EM2, AZX_VS_EM2_L1SEN, value); snd_hdac_chip_updatel(&adev->base.core, VS_EM2, AZX_VS_EM2_L1SEN, value);
} }