arm64: perf: Move PMUv3 driver to drivers/perf
Having the ARM PMUv3 driver sitting in arch/arm64/kernel is getting in the way of being able to use perf on ARMv8 cores running a 32bit kernel, such as 32bit KVM guests. This patch moves it into drivers/perf/arm_pmuv3.c, with an include file in include/linux/perf/arm_pmuv3.h. The only thing left in arch/arm64 is some mundane perf stuff. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Zaid Al-Bassam <zalbassam@google.com> Tested-by: Florian Fainelli <f.fainelli@gmail.com> Link: https://lore.kernel.org/r/20230317195027.3746949-2-zalbassam@google.com Signed-off-by: Will Deacon <will@kernel.org>
This commit is contained in:
Marc Zyngier
Will Deacon
parent
e8d018dd02
commit
7755cec63a
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@ -9,255 +9,6 @@
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#include <asm/stack_pointer.h>
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#include <asm/ptrace.h>
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#define ARMV8_PMU_MAX_COUNTERS 32
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#define ARMV8_PMU_COUNTER_MASK (ARMV8_PMU_MAX_COUNTERS - 1)
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/*
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* Common architectural and microarchitectural event numbers.
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*/
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#define ARMV8_PMUV3_PERFCTR_SW_INCR 0x0000
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#define ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL 0x0001
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#define ARMV8_PMUV3_PERFCTR_L1I_TLB_REFILL 0x0002
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#define ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL 0x0003
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#define ARMV8_PMUV3_PERFCTR_L1D_CACHE 0x0004
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#define ARMV8_PMUV3_PERFCTR_L1D_TLB_REFILL 0x0005
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#define ARMV8_PMUV3_PERFCTR_LD_RETIRED 0x0006
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#define ARMV8_PMUV3_PERFCTR_ST_RETIRED 0x0007
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#define ARMV8_PMUV3_PERFCTR_INST_RETIRED 0x0008
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#define ARMV8_PMUV3_PERFCTR_EXC_TAKEN 0x0009
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#define ARMV8_PMUV3_PERFCTR_EXC_RETURN 0x000A
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#define ARMV8_PMUV3_PERFCTR_CID_WRITE_RETIRED 0x000B
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#define ARMV8_PMUV3_PERFCTR_PC_WRITE_RETIRED 0x000C
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#define ARMV8_PMUV3_PERFCTR_BR_IMMED_RETIRED 0x000D
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#define ARMV8_PMUV3_PERFCTR_BR_RETURN_RETIRED 0x000E
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#define ARMV8_PMUV3_PERFCTR_UNALIGNED_LDST_RETIRED 0x000F
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#define ARMV8_PMUV3_PERFCTR_BR_MIS_PRED 0x0010
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#define ARMV8_PMUV3_PERFCTR_CPU_CYCLES 0x0011
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#define ARMV8_PMUV3_PERFCTR_BR_PRED 0x0012
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#define ARMV8_PMUV3_PERFCTR_MEM_ACCESS 0x0013
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#define ARMV8_PMUV3_PERFCTR_L1I_CACHE 0x0014
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#define ARMV8_PMUV3_PERFCTR_L1D_CACHE_WB 0x0015
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#define ARMV8_PMUV3_PERFCTR_L2D_CACHE 0x0016
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#define ARMV8_PMUV3_PERFCTR_L2D_CACHE_REFILL 0x0017
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#define ARMV8_PMUV3_PERFCTR_L2D_CACHE_WB 0x0018
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#define ARMV8_PMUV3_PERFCTR_BUS_ACCESS 0x0019
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#define ARMV8_PMUV3_PERFCTR_MEMORY_ERROR 0x001A
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#define ARMV8_PMUV3_PERFCTR_INST_SPEC 0x001B
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#define ARMV8_PMUV3_PERFCTR_TTBR_WRITE_RETIRED 0x001C
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#define ARMV8_PMUV3_PERFCTR_BUS_CYCLES 0x001D
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#define ARMV8_PMUV3_PERFCTR_CHAIN 0x001E
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#define ARMV8_PMUV3_PERFCTR_L1D_CACHE_ALLOCATE 0x001F
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#define ARMV8_PMUV3_PERFCTR_L2D_CACHE_ALLOCATE 0x0020
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#define ARMV8_PMUV3_PERFCTR_BR_RETIRED 0x0021
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#define ARMV8_PMUV3_PERFCTR_BR_MIS_PRED_RETIRED 0x0022
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#define ARMV8_PMUV3_PERFCTR_STALL_FRONTEND 0x0023
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#define ARMV8_PMUV3_PERFCTR_STALL_BACKEND 0x0024
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#define ARMV8_PMUV3_PERFCTR_L1D_TLB 0x0025
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#define ARMV8_PMUV3_PERFCTR_L1I_TLB 0x0026
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#define ARMV8_PMUV3_PERFCTR_L2I_CACHE 0x0027
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#define ARMV8_PMUV3_PERFCTR_L2I_CACHE_REFILL 0x0028
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#define ARMV8_PMUV3_PERFCTR_L3D_CACHE_ALLOCATE 0x0029
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#define ARMV8_PMUV3_PERFCTR_L3D_CACHE_REFILL 0x002A
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#define ARMV8_PMUV3_PERFCTR_L3D_CACHE 0x002B
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#define ARMV8_PMUV3_PERFCTR_L3D_CACHE_WB 0x002C
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#define ARMV8_PMUV3_PERFCTR_L2D_TLB_REFILL 0x002D
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#define ARMV8_PMUV3_PERFCTR_L2I_TLB_REFILL 0x002E
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#define ARMV8_PMUV3_PERFCTR_L2D_TLB 0x002F
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#define ARMV8_PMUV3_PERFCTR_L2I_TLB 0x0030
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#define ARMV8_PMUV3_PERFCTR_REMOTE_ACCESS 0x0031
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#define ARMV8_PMUV3_PERFCTR_LL_CACHE 0x0032
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#define ARMV8_PMUV3_PERFCTR_LL_CACHE_MISS 0x0033
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#define ARMV8_PMUV3_PERFCTR_DTLB_WALK 0x0034
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#define ARMV8_PMUV3_PERFCTR_ITLB_WALK 0x0035
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#define ARMV8_PMUV3_PERFCTR_LL_CACHE_RD 0x0036
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#define ARMV8_PMUV3_PERFCTR_LL_CACHE_MISS_RD 0x0037
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#define ARMV8_PMUV3_PERFCTR_REMOTE_ACCESS_RD 0x0038
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#define ARMV8_PMUV3_PERFCTR_L1D_CACHE_LMISS_RD 0x0039
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#define ARMV8_PMUV3_PERFCTR_OP_RETIRED 0x003A
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#define ARMV8_PMUV3_PERFCTR_OP_SPEC 0x003B
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#define ARMV8_PMUV3_PERFCTR_STALL 0x003C
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#define ARMV8_PMUV3_PERFCTR_STALL_SLOT_BACKEND 0x003D
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#define ARMV8_PMUV3_PERFCTR_STALL_SLOT_FRONTEND 0x003E
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#define ARMV8_PMUV3_PERFCTR_STALL_SLOT 0x003F
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/* Statistical profiling extension microarchitectural events */
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#define ARMV8_SPE_PERFCTR_SAMPLE_POP 0x4000
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#define ARMV8_SPE_PERFCTR_SAMPLE_FEED 0x4001
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#define ARMV8_SPE_PERFCTR_SAMPLE_FILTRATE 0x4002
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#define ARMV8_SPE_PERFCTR_SAMPLE_COLLISION 0x4003
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/* AMUv1 architecture events */
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#define ARMV8_AMU_PERFCTR_CNT_CYCLES 0x4004
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#define ARMV8_AMU_PERFCTR_STALL_BACKEND_MEM 0x4005
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/* long-latency read miss events */
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#define ARMV8_PMUV3_PERFCTR_L1I_CACHE_LMISS 0x4006
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#define ARMV8_PMUV3_PERFCTR_L2D_CACHE_LMISS_RD 0x4009
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#define ARMV8_PMUV3_PERFCTR_L2I_CACHE_LMISS 0x400A
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#define ARMV8_PMUV3_PERFCTR_L3D_CACHE_LMISS_RD 0x400B
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/* Trace buffer events */
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#define ARMV8_PMUV3_PERFCTR_TRB_WRAP 0x400C
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#define ARMV8_PMUV3_PERFCTR_TRB_TRIG 0x400E
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/* Trace unit events */
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#define ARMV8_PMUV3_PERFCTR_TRCEXTOUT0 0x4010
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#define ARMV8_PMUV3_PERFCTR_TRCEXTOUT1 0x4011
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#define ARMV8_PMUV3_PERFCTR_TRCEXTOUT2 0x4012
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#define ARMV8_PMUV3_PERFCTR_TRCEXTOUT3 0x4013
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#define ARMV8_PMUV3_PERFCTR_CTI_TRIGOUT4 0x4018
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#define ARMV8_PMUV3_PERFCTR_CTI_TRIGOUT5 0x4019
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#define ARMV8_PMUV3_PERFCTR_CTI_TRIGOUT6 0x401A
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#define ARMV8_PMUV3_PERFCTR_CTI_TRIGOUT7 0x401B
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/* additional latency from alignment events */
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#define ARMV8_PMUV3_PERFCTR_LDST_ALIGN_LAT 0x4020
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#define ARMV8_PMUV3_PERFCTR_LD_ALIGN_LAT 0x4021
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#define ARMV8_PMUV3_PERFCTR_ST_ALIGN_LAT 0x4022
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/* Armv8.5 Memory Tagging Extension events */
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#define ARMV8_MTE_PERFCTR_MEM_ACCESS_CHECKED 0x4024
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#define ARMV8_MTE_PERFCTR_MEM_ACCESS_CHECKED_RD 0x4025
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#define ARMV8_MTE_PERFCTR_MEM_ACCESS_CHECKED_WR 0x4026
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/* ARMv8 recommended implementation defined event types */
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#define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD 0x0040
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#define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR 0x0041
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#define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_RD 0x0042
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#define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_WR 0x0043
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#define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_INNER 0x0044
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#define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_OUTER 0x0045
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#define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WB_VICTIM 0x0046
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#define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WB_CLEAN 0x0047
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#define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_INVAL 0x0048
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#define ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_RD 0x004C
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#define ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_WR 0x004D
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#define ARMV8_IMPDEF_PERFCTR_L1D_TLB_RD 0x004E
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#define ARMV8_IMPDEF_PERFCTR_L1D_TLB_WR 0x004F
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#define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_RD 0x0050
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#define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_WR 0x0051
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#define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_REFILL_RD 0x0052
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#define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_REFILL_WR 0x0053
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#define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_WB_VICTIM 0x0056
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#define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_WB_CLEAN 0x0057
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#define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_INVAL 0x0058
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#define ARMV8_IMPDEF_PERFCTR_L2D_TLB_REFILL_RD 0x005C
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#define ARMV8_IMPDEF_PERFCTR_L2D_TLB_REFILL_WR 0x005D
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#define ARMV8_IMPDEF_PERFCTR_L2D_TLB_RD 0x005E
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#define ARMV8_IMPDEF_PERFCTR_L2D_TLB_WR 0x005F
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#define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_RD 0x0060
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#define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_WR 0x0061
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#define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_SHARED 0x0062
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#define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_NOT_SHARED 0x0063
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#define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_NORMAL 0x0064
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#define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_PERIPH 0x0065
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#define ARMV8_IMPDEF_PERFCTR_MEM_ACCESS_RD 0x0066
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#define ARMV8_IMPDEF_PERFCTR_MEM_ACCESS_WR 0x0067
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#define ARMV8_IMPDEF_PERFCTR_UNALIGNED_LD_SPEC 0x0068
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#define ARMV8_IMPDEF_PERFCTR_UNALIGNED_ST_SPEC 0x0069
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#define ARMV8_IMPDEF_PERFCTR_UNALIGNED_LDST_SPEC 0x006A
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#define ARMV8_IMPDEF_PERFCTR_LDREX_SPEC 0x006C
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#define ARMV8_IMPDEF_PERFCTR_STREX_PASS_SPEC 0x006D
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#define ARMV8_IMPDEF_PERFCTR_STREX_FAIL_SPEC 0x006E
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#define ARMV8_IMPDEF_PERFCTR_STREX_SPEC 0x006F
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#define ARMV8_IMPDEF_PERFCTR_LD_SPEC 0x0070
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#define ARMV8_IMPDEF_PERFCTR_ST_SPEC 0x0071
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#define ARMV8_IMPDEF_PERFCTR_LDST_SPEC 0x0072
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#define ARMV8_IMPDEF_PERFCTR_DP_SPEC 0x0073
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#define ARMV8_IMPDEF_PERFCTR_ASE_SPEC 0x0074
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#define ARMV8_IMPDEF_PERFCTR_VFP_SPEC 0x0075
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#define ARMV8_IMPDEF_PERFCTR_PC_WRITE_SPEC 0x0076
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#define ARMV8_IMPDEF_PERFCTR_CRYPTO_SPEC 0x0077
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#define ARMV8_IMPDEF_PERFCTR_BR_IMMED_SPEC 0x0078
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#define ARMV8_IMPDEF_PERFCTR_BR_RETURN_SPEC 0x0079
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#define ARMV8_IMPDEF_PERFCTR_BR_INDIRECT_SPEC 0x007A
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#define ARMV8_IMPDEF_PERFCTR_ISB_SPEC 0x007C
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#define ARMV8_IMPDEF_PERFCTR_DSB_SPEC 0x007D
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#define ARMV8_IMPDEF_PERFCTR_DMB_SPEC 0x007E
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#define ARMV8_IMPDEF_PERFCTR_EXC_UNDEF 0x0081
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#define ARMV8_IMPDEF_PERFCTR_EXC_SVC 0x0082
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#define ARMV8_IMPDEF_PERFCTR_EXC_PABORT 0x0083
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#define ARMV8_IMPDEF_PERFCTR_EXC_DABORT 0x0084
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#define ARMV8_IMPDEF_PERFCTR_EXC_IRQ 0x0086
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#define ARMV8_IMPDEF_PERFCTR_EXC_FIQ 0x0087
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#define ARMV8_IMPDEF_PERFCTR_EXC_SMC 0x0088
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#define ARMV8_IMPDEF_PERFCTR_EXC_HVC 0x008A
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#define ARMV8_IMPDEF_PERFCTR_EXC_TRAP_PABORT 0x008B
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#define ARMV8_IMPDEF_PERFCTR_EXC_TRAP_DABORT 0x008C
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#define ARMV8_IMPDEF_PERFCTR_EXC_TRAP_OTHER 0x008D
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#define ARMV8_IMPDEF_PERFCTR_EXC_TRAP_IRQ 0x008E
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#define ARMV8_IMPDEF_PERFCTR_EXC_TRAP_FIQ 0x008F
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#define ARMV8_IMPDEF_PERFCTR_RC_LD_SPEC 0x0090
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#define ARMV8_IMPDEF_PERFCTR_RC_ST_SPEC 0x0091
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#define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_RD 0x00A0
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#define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_WR 0x00A1
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#define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_REFILL_RD 0x00A2
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#define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_REFILL_WR 0x00A3
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#define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_WB_VICTIM 0x00A6
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#define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_WB_CLEAN 0x00A7
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#define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_INVAL 0x00A8
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/*
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* Per-CPU PMCR: config reg
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*/
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#define ARMV8_PMU_PMCR_E (1 << 0) /* Enable all counters */
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#define ARMV8_PMU_PMCR_P (1 << 1) /* Reset all counters */
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#define ARMV8_PMU_PMCR_C (1 << 2) /* Cycle counter reset */
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#define ARMV8_PMU_PMCR_D (1 << 3) /* CCNT counts every 64th cpu cycle */
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#define ARMV8_PMU_PMCR_X (1 << 4) /* Export to ETM */
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#define ARMV8_PMU_PMCR_DP (1 << 5) /* Disable CCNT if non-invasive debug*/
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#define ARMV8_PMU_PMCR_LC (1 << 6) /* Overflow on 64 bit cycle counter */
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#define ARMV8_PMU_PMCR_LP (1 << 7) /* Long event counter enable */
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#define ARMV8_PMU_PMCR_N_SHIFT 11 /* Number of counters supported */
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#define ARMV8_PMU_PMCR_N_MASK 0x1f
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#define ARMV8_PMU_PMCR_MASK 0xff /* Mask for writable bits */
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/*
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* PMOVSR: counters overflow flag status reg
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*/
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#define ARMV8_PMU_OVSR_MASK 0xffffffff /* Mask for writable bits */
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#define ARMV8_PMU_OVERFLOWED_MASK ARMV8_PMU_OVSR_MASK
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/*
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* PMXEVTYPER: Event selection reg
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*/
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#define ARMV8_PMU_EVTYPE_MASK 0xc800ffff /* Mask for writable bits */
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#define ARMV8_PMU_EVTYPE_EVENT 0xffff /* Mask for EVENT bits */
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/*
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* Event filters for PMUv3
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*/
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#define ARMV8_PMU_EXCLUDE_EL1 (1U << 31)
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#define ARMV8_PMU_EXCLUDE_EL0 (1U << 30)
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#define ARMV8_PMU_INCLUDE_EL2 (1U << 27)
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/*
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* PMUSERENR: user enable reg
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*/
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#define ARMV8_PMU_USERENR_MASK 0xf /* Mask for writable bits */
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#define ARMV8_PMU_USERENR_EN (1 << 0) /* PMU regs can be accessed at EL0 */
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#define ARMV8_PMU_USERENR_SW (1 << 1) /* PMSWINC can be written at EL0 */
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#define ARMV8_PMU_USERENR_CR (1 << 2) /* Cycle counter can be read at EL0 */
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#define ARMV8_PMU_USERENR_ER (1 << 3) /* Event counter can be read at EL0 */
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/* PMMIR_EL1.SLOTS mask */
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#define ARMV8_PMU_SLOTS_MASK 0xff
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#define ARMV8_PMU_BUS_SLOTS_SHIFT 8
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#define ARMV8_PMU_BUS_SLOTS_MASK 0xff
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#define ARMV8_PMU_BUS_WIDTH_SHIFT 16
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#define ARMV8_PMU_BUS_WIDTH_MASK 0xf
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#ifdef CONFIG_PERF_EVENTS
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struct pt_regs;
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extern unsigned long perf_instruction_pointer(struct pt_regs *regs);
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@ -45,7 +45,6 @@ obj-$(CONFIG_FUNCTION_TRACER) += ftrace.o entry-ftrace.o
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obj-$(CONFIG_MODULES) += module.o
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obj-$(CONFIG_ARM64_MODULE_PLTS) += module-plts.o
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obj-$(CONFIG_PERF_EVENTS) += perf_regs.o perf_callchain.o
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obj-$(CONFIG_HW_PERF_EVENTS) += perf_event.o
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obj-$(CONFIG_HAVE_HW_BREAKPOINT) += hw_breakpoint.o
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obj-$(CONFIG_CPU_PM) += sleep.o suspend.o
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obj-$(CONFIG_CPU_IDLE) += cpuidle.o
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@ -100,6 +100,17 @@ config ARM_SMMU_V3_PMU
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through the SMMU and allow the resulting information to be filtered
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based on the Stream ID of the corresponding master.
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config ARM_PMUV3
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depends on HW_PERF_EVENTS && ARM64
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bool "ARM PMUv3 support" if !ARM64
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default y
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help
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Say y if you want to use the ARM performance monitor unit (PMU)
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version 3. The PMUv3 is the CPU performance monitors on ARMv8
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(aarch32 and aarch64) systems that implement the PMUv3
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architecture.
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Currently, PMUv3 is only supported on aarch64 (arm64)
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config ARM_DSU_PMU
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tristate "ARM DynamIQ Shared Unit (DSU) PMU"
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depends on ARM64
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|
|
@ -5,6 +5,7 @@ obj-$(CONFIG_ARM_CMN) += arm-cmn.o
|
|||
obj-$(CONFIG_ARM_DSU_PMU) += arm_dsu_pmu.o
|
||||
obj-$(CONFIG_ARM_PMU) += arm_pmu.o arm_pmu_platform.o
|
||||
obj-$(CONFIG_ARM_PMU_ACPI) += arm_pmu_acpi.o
|
||||
obj-$(CONFIG_ARM_PMUV3) += arm_pmuv3.o
|
||||
obj-$(CONFIG_ARM_SMMU_V3_PMU) += arm_smmuv3_pmu.o
|
||||
obj-$(CONFIG_FSL_IMX8_DDR_PMU) += fsl_imx8_ddr_perf.o
|
||||
obj-$(CONFIG_HISI_PMU) += hisilicon/
|
||||
|
|
|
|||
|
|
@ -20,6 +20,7 @@
|
|||
#include <linux/kvm_host.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/perf/arm_pmu.h>
|
||||
#include <linux/perf/arm_pmuv3.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/sched_clock.h>
|
||||
#include <linux/smp.h>
|
||||
|
|
@ -8,7 +8,7 @@
|
|||
#define __ASM_ARM_KVM_PMU_H
|
||||
|
||||
#include <linux/perf_event.h>
|
||||
#include <asm/perf_event.h>
|
||||
#include <linux/perf/arm_pmuv3.h>
|
||||
|
||||
#define ARMV8_PMU_CYCLE_IDX (ARMV8_PMU_MAX_COUNTERS - 1)
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,258 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (C) 2012 ARM Ltd.
|
||||
*/
|
||||
|
||||
#ifndef __PERF_ARM_PMUV3_H
|
||||
#define __PERF_ARM_PMUV3_H
|
||||
|
||||
#define ARMV8_PMU_MAX_COUNTERS 32
|
||||
#define ARMV8_PMU_COUNTER_MASK (ARMV8_PMU_MAX_COUNTERS - 1)
|
||||
|
||||
/*
|
||||
* Common architectural and microarchitectural event numbers.
|
||||
*/
|
||||
#define ARMV8_PMUV3_PERFCTR_SW_INCR 0x0000
|
||||
#define ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL 0x0001
|
||||
#define ARMV8_PMUV3_PERFCTR_L1I_TLB_REFILL 0x0002
|
||||
#define ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL 0x0003
|
||||
#define ARMV8_PMUV3_PERFCTR_L1D_CACHE 0x0004
|
||||
#define ARMV8_PMUV3_PERFCTR_L1D_TLB_REFILL 0x0005
|
||||
#define ARMV8_PMUV3_PERFCTR_LD_RETIRED 0x0006
|
||||
#define ARMV8_PMUV3_PERFCTR_ST_RETIRED 0x0007
|
||||
#define ARMV8_PMUV3_PERFCTR_INST_RETIRED 0x0008
|
||||
#define ARMV8_PMUV3_PERFCTR_EXC_TAKEN 0x0009
|
||||
#define ARMV8_PMUV3_PERFCTR_EXC_RETURN 0x000A
|
||||
#define ARMV8_PMUV3_PERFCTR_CID_WRITE_RETIRED 0x000B
|
||||
#define ARMV8_PMUV3_PERFCTR_PC_WRITE_RETIRED 0x000C
|
||||
#define ARMV8_PMUV3_PERFCTR_BR_IMMED_RETIRED 0x000D
|
||||
#define ARMV8_PMUV3_PERFCTR_BR_RETURN_RETIRED 0x000E
|
||||
#define ARMV8_PMUV3_PERFCTR_UNALIGNED_LDST_RETIRED 0x000F
|
||||
#define ARMV8_PMUV3_PERFCTR_BR_MIS_PRED 0x0010
|
||||
#define ARMV8_PMUV3_PERFCTR_CPU_CYCLES 0x0011
|
||||
#define ARMV8_PMUV3_PERFCTR_BR_PRED 0x0012
|
||||
#define ARMV8_PMUV3_PERFCTR_MEM_ACCESS 0x0013
|
||||
#define ARMV8_PMUV3_PERFCTR_L1I_CACHE 0x0014
|
||||
#define ARMV8_PMUV3_PERFCTR_L1D_CACHE_WB 0x0015
|
||||
#define ARMV8_PMUV3_PERFCTR_L2D_CACHE 0x0016
|
||||
#define ARMV8_PMUV3_PERFCTR_L2D_CACHE_REFILL 0x0017
|
||||
#define ARMV8_PMUV3_PERFCTR_L2D_CACHE_WB 0x0018
|
||||
#define ARMV8_PMUV3_PERFCTR_BUS_ACCESS 0x0019
|
||||
#define ARMV8_PMUV3_PERFCTR_MEMORY_ERROR 0x001A
|
||||
#define ARMV8_PMUV3_PERFCTR_INST_SPEC 0x001B
|
||||
#define ARMV8_PMUV3_PERFCTR_TTBR_WRITE_RETIRED 0x001C
|
||||
#define ARMV8_PMUV3_PERFCTR_BUS_CYCLES 0x001D
|
||||
#define ARMV8_PMUV3_PERFCTR_CHAIN 0x001E
|
||||
#define ARMV8_PMUV3_PERFCTR_L1D_CACHE_ALLOCATE 0x001F
|
||||
#define ARMV8_PMUV3_PERFCTR_L2D_CACHE_ALLOCATE 0x0020
|
||||
#define ARMV8_PMUV3_PERFCTR_BR_RETIRED 0x0021
|
||||
#define ARMV8_PMUV3_PERFCTR_BR_MIS_PRED_RETIRED 0x0022
|
||||
#define ARMV8_PMUV3_PERFCTR_STALL_FRONTEND 0x0023
|
||||
#define ARMV8_PMUV3_PERFCTR_STALL_BACKEND 0x0024
|
||||
#define ARMV8_PMUV3_PERFCTR_L1D_TLB 0x0025
|
||||
#define ARMV8_PMUV3_PERFCTR_L1I_TLB 0x0026
|
||||
#define ARMV8_PMUV3_PERFCTR_L2I_CACHE 0x0027
|
||||
#define ARMV8_PMUV3_PERFCTR_L2I_CACHE_REFILL 0x0028
|
||||
#define ARMV8_PMUV3_PERFCTR_L3D_CACHE_ALLOCATE 0x0029
|
||||
#define ARMV8_PMUV3_PERFCTR_L3D_CACHE_REFILL 0x002A
|
||||
#define ARMV8_PMUV3_PERFCTR_L3D_CACHE 0x002B
|
||||
#define ARMV8_PMUV3_PERFCTR_L3D_CACHE_WB 0x002C
|
||||
#define ARMV8_PMUV3_PERFCTR_L2D_TLB_REFILL 0x002D
|
||||
#define ARMV8_PMUV3_PERFCTR_L2I_TLB_REFILL 0x002E
|
||||
#define ARMV8_PMUV3_PERFCTR_L2D_TLB 0x002F
|
||||
#define ARMV8_PMUV3_PERFCTR_L2I_TLB 0x0030
|
||||
#define ARMV8_PMUV3_PERFCTR_REMOTE_ACCESS 0x0031
|
||||
#define ARMV8_PMUV3_PERFCTR_LL_CACHE 0x0032
|
||||
#define ARMV8_PMUV3_PERFCTR_LL_CACHE_MISS 0x0033
|
||||
#define ARMV8_PMUV3_PERFCTR_DTLB_WALK 0x0034
|
||||
#define ARMV8_PMUV3_PERFCTR_ITLB_WALK 0x0035
|
||||
#define ARMV8_PMUV3_PERFCTR_LL_CACHE_RD 0x0036
|
||||
#define ARMV8_PMUV3_PERFCTR_LL_CACHE_MISS_RD 0x0037
|
||||
#define ARMV8_PMUV3_PERFCTR_REMOTE_ACCESS_RD 0x0038
|
||||
#define ARMV8_PMUV3_PERFCTR_L1D_CACHE_LMISS_RD 0x0039
|
||||
#define ARMV8_PMUV3_PERFCTR_OP_RETIRED 0x003A
|
||||
#define ARMV8_PMUV3_PERFCTR_OP_SPEC 0x003B
|
||||
#define ARMV8_PMUV3_PERFCTR_STALL 0x003C
|
||||
#define ARMV8_PMUV3_PERFCTR_STALL_SLOT_BACKEND 0x003D
|
||||
#define ARMV8_PMUV3_PERFCTR_STALL_SLOT_FRONTEND 0x003E
|
||||
#define ARMV8_PMUV3_PERFCTR_STALL_SLOT 0x003F
|
||||
|
||||
/* Statistical profiling extension microarchitectural events */
|
||||
#define ARMV8_SPE_PERFCTR_SAMPLE_POP 0x4000
|
||||
#define ARMV8_SPE_PERFCTR_SAMPLE_FEED 0x4001
|
||||
#define ARMV8_SPE_PERFCTR_SAMPLE_FILTRATE 0x4002
|
||||
#define ARMV8_SPE_PERFCTR_SAMPLE_COLLISION 0x4003
|
||||
|
||||
/* AMUv1 architecture events */
|
||||
#define ARMV8_AMU_PERFCTR_CNT_CYCLES 0x4004
|
||||
#define ARMV8_AMU_PERFCTR_STALL_BACKEND_MEM 0x4005
|
||||
|
||||
/* long-latency read miss events */
|
||||
#define ARMV8_PMUV3_PERFCTR_L1I_CACHE_LMISS 0x4006
|
||||
#define ARMV8_PMUV3_PERFCTR_L2D_CACHE_LMISS_RD 0x4009
|
||||
#define ARMV8_PMUV3_PERFCTR_L2I_CACHE_LMISS 0x400A
|
||||
#define ARMV8_PMUV3_PERFCTR_L3D_CACHE_LMISS_RD 0x400B
|
||||
|
||||
/* Trace buffer events */
|
||||
#define ARMV8_PMUV3_PERFCTR_TRB_WRAP 0x400C
|
||||
#define ARMV8_PMUV3_PERFCTR_TRB_TRIG 0x400E
|
||||
|
||||
/* Trace unit events */
|
||||
#define ARMV8_PMUV3_PERFCTR_TRCEXTOUT0 0x4010
|
||||
#define ARMV8_PMUV3_PERFCTR_TRCEXTOUT1 0x4011
|
||||
#define ARMV8_PMUV3_PERFCTR_TRCEXTOUT2 0x4012
|
||||
#define ARMV8_PMUV3_PERFCTR_TRCEXTOUT3 0x4013
|
||||
#define ARMV8_PMUV3_PERFCTR_CTI_TRIGOUT4 0x4018
|
||||
#define ARMV8_PMUV3_PERFCTR_CTI_TRIGOUT5 0x4019
|
||||
#define ARMV8_PMUV3_PERFCTR_CTI_TRIGOUT6 0x401A
|
||||
#define ARMV8_PMUV3_PERFCTR_CTI_TRIGOUT7 0x401B
|
||||
|
||||
/* additional latency from alignment events */
|
||||
#define ARMV8_PMUV3_PERFCTR_LDST_ALIGN_LAT 0x4020
|
||||
#define ARMV8_PMUV3_PERFCTR_LD_ALIGN_LAT 0x4021
|
||||
#define ARMV8_PMUV3_PERFCTR_ST_ALIGN_LAT 0x4022
|
||||
|
||||
/* Armv8.5 Memory Tagging Extension events */
|
||||
#define ARMV8_MTE_PERFCTR_MEM_ACCESS_CHECKED 0x4024
|
||||
#define ARMV8_MTE_PERFCTR_MEM_ACCESS_CHECKED_RD 0x4025
|
||||
#define ARMV8_MTE_PERFCTR_MEM_ACCESS_CHECKED_WR 0x4026
|
||||
|
||||
/* ARMv8 recommended implementation defined event types */
|
||||
#define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD 0x0040
|
||||
#define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR 0x0041
|
||||
#define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_RD 0x0042
|
||||
#define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_WR 0x0043
|
||||
#define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_INNER 0x0044
|
||||
#define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_OUTER 0x0045
|
||||
#define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WB_VICTIM 0x0046
|
||||
#define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WB_CLEAN 0x0047
|
||||
#define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_INVAL 0x0048
|
||||
|
||||
#define ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_RD 0x004C
|
||||
#define ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_WR 0x004D
|
||||
#define ARMV8_IMPDEF_PERFCTR_L1D_TLB_RD 0x004E
|
||||
#define ARMV8_IMPDEF_PERFCTR_L1D_TLB_WR 0x004F
|
||||
#define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_RD 0x0050
|
||||
#define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_WR 0x0051
|
||||
#define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_REFILL_RD 0x0052
|
||||
#define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_REFILL_WR 0x0053
|
||||
|
||||
#define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_WB_VICTIM 0x0056
|
||||
#define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_WB_CLEAN 0x0057
|
||||
#define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_INVAL 0x0058
|
||||
|
||||
#define ARMV8_IMPDEF_PERFCTR_L2D_TLB_REFILL_RD 0x005C
|
||||
#define ARMV8_IMPDEF_PERFCTR_L2D_TLB_REFILL_WR 0x005D
|
||||
#define ARMV8_IMPDEF_PERFCTR_L2D_TLB_RD 0x005E
|
||||
#define ARMV8_IMPDEF_PERFCTR_L2D_TLB_WR 0x005F
|
||||
#define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_RD 0x0060
|
||||
#define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_WR 0x0061
|
||||
#define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_SHARED 0x0062
|
||||
#define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_NOT_SHARED 0x0063
|
||||
#define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_NORMAL 0x0064
|
||||
#define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_PERIPH 0x0065
|
||||
#define ARMV8_IMPDEF_PERFCTR_MEM_ACCESS_RD 0x0066
|
||||
#define ARMV8_IMPDEF_PERFCTR_MEM_ACCESS_WR 0x0067
|
||||
#define ARMV8_IMPDEF_PERFCTR_UNALIGNED_LD_SPEC 0x0068
|
||||
#define ARMV8_IMPDEF_PERFCTR_UNALIGNED_ST_SPEC 0x0069
|
||||
#define ARMV8_IMPDEF_PERFCTR_UNALIGNED_LDST_SPEC 0x006A
|
||||
|
||||
#define ARMV8_IMPDEF_PERFCTR_LDREX_SPEC 0x006C
|
||||
#define ARMV8_IMPDEF_PERFCTR_STREX_PASS_SPEC 0x006D
|
||||
#define ARMV8_IMPDEF_PERFCTR_STREX_FAIL_SPEC 0x006E
|
||||
#define ARMV8_IMPDEF_PERFCTR_STREX_SPEC 0x006F
|
||||
#define ARMV8_IMPDEF_PERFCTR_LD_SPEC 0x0070
|
||||
#define ARMV8_IMPDEF_PERFCTR_ST_SPEC 0x0071
|
||||
#define ARMV8_IMPDEF_PERFCTR_LDST_SPEC 0x0072
|
||||
#define ARMV8_IMPDEF_PERFCTR_DP_SPEC 0x0073
|
||||
#define ARMV8_IMPDEF_PERFCTR_ASE_SPEC 0x0074
|
||||
#define ARMV8_IMPDEF_PERFCTR_VFP_SPEC 0x0075
|
||||
#define ARMV8_IMPDEF_PERFCTR_PC_WRITE_SPEC 0x0076
|
||||
#define ARMV8_IMPDEF_PERFCTR_CRYPTO_SPEC 0x0077
|
||||
#define ARMV8_IMPDEF_PERFCTR_BR_IMMED_SPEC 0x0078
|
||||
#define ARMV8_IMPDEF_PERFCTR_BR_RETURN_SPEC 0x0079
|
||||
#define ARMV8_IMPDEF_PERFCTR_BR_INDIRECT_SPEC 0x007A
|
||||
|
||||
#define ARMV8_IMPDEF_PERFCTR_ISB_SPEC 0x007C
|
||||
#define ARMV8_IMPDEF_PERFCTR_DSB_SPEC 0x007D
|
||||
#define ARMV8_IMPDEF_PERFCTR_DMB_SPEC 0x007E
|
||||
|
||||
#define ARMV8_IMPDEF_PERFCTR_EXC_UNDEF 0x0081
|
||||
#define ARMV8_IMPDEF_PERFCTR_EXC_SVC 0x0082
|
||||
#define ARMV8_IMPDEF_PERFCTR_EXC_PABORT 0x0083
|
||||
#define ARMV8_IMPDEF_PERFCTR_EXC_DABORT 0x0084
|
||||
|
||||
#define ARMV8_IMPDEF_PERFCTR_EXC_IRQ 0x0086
|
||||
#define ARMV8_IMPDEF_PERFCTR_EXC_FIQ 0x0087
|
||||
#define ARMV8_IMPDEF_PERFCTR_EXC_SMC 0x0088
|
||||
|
||||
#define ARMV8_IMPDEF_PERFCTR_EXC_HVC 0x008A
|
||||
#define ARMV8_IMPDEF_PERFCTR_EXC_TRAP_PABORT 0x008B
|
||||
#define ARMV8_IMPDEF_PERFCTR_EXC_TRAP_DABORT 0x008C
|
||||
#define ARMV8_IMPDEF_PERFCTR_EXC_TRAP_OTHER 0x008D
|
||||
#define ARMV8_IMPDEF_PERFCTR_EXC_TRAP_IRQ 0x008E
|
||||
#define ARMV8_IMPDEF_PERFCTR_EXC_TRAP_FIQ 0x008F
|
||||
#define ARMV8_IMPDEF_PERFCTR_RC_LD_SPEC 0x0090
|
||||
#define ARMV8_IMPDEF_PERFCTR_RC_ST_SPEC 0x0091
|
||||
|
||||
#define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_RD 0x00A0
|
||||
#define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_WR 0x00A1
|
||||
#define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_REFILL_RD 0x00A2
|
||||
#define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_REFILL_WR 0x00A3
|
||||
|
||||
#define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_WB_VICTIM 0x00A6
|
||||
#define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_WB_CLEAN 0x00A7
|
||||
#define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_INVAL 0x00A8
|
||||
|
||||
/*
|
||||
* Per-CPU PMCR: config reg
|
||||
*/
|
||||
#define ARMV8_PMU_PMCR_E (1 << 0) /* Enable all counters */
|
||||
#define ARMV8_PMU_PMCR_P (1 << 1) /* Reset all counters */
|
||||
#define ARMV8_PMU_PMCR_C (1 << 2) /* Cycle counter reset */
|
||||
#define ARMV8_PMU_PMCR_D (1 << 3) /* CCNT counts every 64th cpu cycle */
|
||||
#define ARMV8_PMU_PMCR_X (1 << 4) /* Export to ETM */
|
||||
#define ARMV8_PMU_PMCR_DP (1 << 5) /* Disable CCNT if non-invasive debug*/
|
||||
#define ARMV8_PMU_PMCR_LC (1 << 6) /* Overflow on 64 bit cycle counter */
|
||||
#define ARMV8_PMU_PMCR_LP (1 << 7) /* Long event counter enable */
|
||||
#define ARMV8_PMU_PMCR_N_SHIFT 11 /* Number of counters supported */
|
||||
#define ARMV8_PMU_PMCR_N_MASK 0x1f
|
||||
#define ARMV8_PMU_PMCR_MASK 0xff /* Mask for writable bits */
|
||||
|
||||
/*
|
||||
* PMOVSR: counters overflow flag status reg
|
||||
*/
|
||||
#define ARMV8_PMU_OVSR_MASK 0xffffffff /* Mask for writable bits */
|
||||
#define ARMV8_PMU_OVERFLOWED_MASK ARMV8_PMU_OVSR_MASK
|
||||
|
||||
/*
|
||||
* PMXEVTYPER: Event selection reg
|
||||
*/
|
||||
#define ARMV8_PMU_EVTYPE_MASK 0xc800ffff /* Mask for writable bits */
|
||||
#define ARMV8_PMU_EVTYPE_EVENT 0xffff /* Mask for EVENT bits */
|
||||
|
||||
/*
|
||||
* Event filters for PMUv3
|
||||
*/
|
||||
#define ARMV8_PMU_EXCLUDE_EL1 (1U << 31)
|
||||
#define ARMV8_PMU_EXCLUDE_EL0 (1U << 30)
|
||||
#define ARMV8_PMU_INCLUDE_EL2 (1U << 27)
|
||||
|
||||
/*
|
||||
* PMUSERENR: user enable reg
|
||||
*/
|
||||
#define ARMV8_PMU_USERENR_MASK 0xf /* Mask for writable bits */
|
||||
#define ARMV8_PMU_USERENR_EN (1 << 0) /* PMU regs can be accessed at EL0 */
|
||||
#define ARMV8_PMU_USERENR_SW (1 << 1) /* PMSWINC can be written at EL0 */
|
||||
#define ARMV8_PMU_USERENR_CR (1 << 2) /* Cycle counter can be read at EL0 */
|
||||
#define ARMV8_PMU_USERENR_ER (1 << 3) /* Event counter can be read at EL0 */
|
||||
|
||||
/* PMMIR_EL1.SLOTS mask */
|
||||
#define ARMV8_PMU_SLOTS_MASK 0xff
|
||||
|
||||
#define ARMV8_PMU_BUS_SLOTS_SHIFT 8
|
||||
#define ARMV8_PMU_BUS_SLOTS_MASK 0xff
|
||||
#define ARMV8_PMU_BUS_WIDTH_SHIFT 16
|
||||
#define ARMV8_PMU_BUS_WIDTH_MASK 0xf
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue