irqchip: Add IMX MU MSI controller driver
The MU block found in a number of Freescale/NXP SoCs supports generating IRQs by writing data to a register. This enables the MU block to be used as a MSI controller, by leveraging the platform-MSI API. Signed-off-by: Frank Li <Frank.Li@nxp.com> [maz: dropped pointless dma-iommu.h and of_pci.h includes] Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20220922161246.20586-4-Frank.Li@nxp.com
This commit is contained in:
Frank Li
Marc Zyngier
parent
334f7d42db
commit
70afdab904
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@ -481,6 +481,20 @@ config IMX_INTMUX
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help
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Support for the i.MX INTMUX interrupt multiplexer.
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config IMX_MU_MSI
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tristate "i.MX MU used as MSI controller"
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depends on OF && HAS_IOMEM
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default m if ARCH_MXC
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select IRQ_DOMAIN
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select IRQ_DOMAIN_HIERARCHY
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select GENERIC_MSI_IRQ_DOMAIN
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help
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Provide a driver for the MU block used as a CPU-to-CPU MSI
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controller. This requires a specially crafted DT to make use
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of this driver.
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If unsure, say N
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config LS1X_IRQ
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bool "Loongson-1 Interrupt Controller"
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depends on MACH_LOONGSON32
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@ -99,6 +99,7 @@ obj-$(CONFIG_RISCV_INTC) += irq-riscv-intc.o
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obj-$(CONFIG_SIFIVE_PLIC) += irq-sifive-plic.o
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obj-$(CONFIG_IMX_IRQSTEER) += irq-imx-irqsteer.o
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obj-$(CONFIG_IMX_INTMUX) += irq-imx-intmux.o
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obj-$(CONFIG_IMX_MU_MSI) += irq-imx-mu-msi.o
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obj-$(CONFIG_MADERA_IRQ) += irq-madera.o
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obj-$(CONFIG_LS1X_IRQ) += irq-ls1x.o
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obj-$(CONFIG_TI_SCI_INTR_IRQCHIP) += irq-ti-sci-intr.o
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@ -0,0 +1,453 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Freescale MU used as MSI controller
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*
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* Copyright (c) 2018 Pengutronix, Oleksij Rempel <o.rempel@pengutronix.de>
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* Copyright 2022 NXP
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* Frank Li <Frank.Li@nxp.com>
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* Peng Fan <peng.fan@nxp.com>
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*
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* Based on drivers/mailbox/imx-mailbox.c
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*/
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#include <linux/clk.h>
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#include <linux/irq.h>
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#include <linux/irqchip.h>
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#include <linux/irqchip/chained_irq.h>
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#include <linux/irqdomain.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/msi.h>
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#include <linux/of_irq.h>
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#include <linux/of_platform.h>
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#include <linux/pm_runtime.h>
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#include <linux/pm_domain.h>
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#include <linux/spinlock.h>
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#define IMX_MU_CHANS 4
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enum imx_mu_xcr {
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IMX_MU_GIER,
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IMX_MU_GCR,
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IMX_MU_TCR,
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IMX_MU_RCR,
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IMX_MU_xCR_MAX,
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};
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enum imx_mu_xsr {
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IMX_MU_SR,
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IMX_MU_GSR,
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IMX_MU_TSR,
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IMX_MU_RSR,
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IMX_MU_xSR_MAX
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};
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enum imx_mu_type {
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IMX_MU_V2 = BIT(1),
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};
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/* Receive Interrupt Enable */
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#define IMX_MU_xCR_RIEn(data, x) ((data->cfg->type) & IMX_MU_V2 ? BIT(x) : BIT(24 + (3 - (x))))
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#define IMX_MU_xSR_RFn(data, x) ((data->cfg->type) & IMX_MU_V2 ? BIT(x) : BIT(24 + (3 - (x))))
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struct imx_mu_dcfg {
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enum imx_mu_type type;
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u32 xTR; /* Transmit Register0 */
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u32 xRR; /* Receive Register0 */
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u32 xSR[IMX_MU_xSR_MAX]; /* Status Registers */
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u32 xCR[IMX_MU_xCR_MAX]; /* Control Registers */
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};
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struct imx_mu_msi {
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raw_spinlock_t lock;
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struct irq_domain *msi_domain;
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void __iomem *regs;
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phys_addr_t msiir_addr;
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const struct imx_mu_dcfg *cfg;
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unsigned long used;
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struct clk *clk;
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};
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static void imx_mu_write(struct imx_mu_msi *msi_data, u32 val, u32 offs)
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{
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iowrite32(val, msi_data->regs + offs);
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}
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static u32 imx_mu_read(struct imx_mu_msi *msi_data, u32 offs)
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{
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return ioread32(msi_data->regs + offs);
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}
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static u32 imx_mu_xcr_rmw(struct imx_mu_msi *msi_data, enum imx_mu_xcr type, u32 set, u32 clr)
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{
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unsigned long flags;
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u32 val;
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raw_spin_lock_irqsave(&msi_data->lock, flags);
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val = imx_mu_read(msi_data, msi_data->cfg->xCR[type]);
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val &= ~clr;
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val |= set;
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imx_mu_write(msi_data, val, msi_data->cfg->xCR[type]);
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raw_spin_unlock_irqrestore(&msi_data->lock, flags);
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return val;
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}
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static void imx_mu_msi_parent_mask_irq(struct irq_data *data)
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{
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struct imx_mu_msi *msi_data = irq_data_get_irq_chip_data(data);
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imx_mu_xcr_rmw(msi_data, IMX_MU_RCR, 0, IMX_MU_xCR_RIEn(msi_data, data->hwirq));
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}
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static void imx_mu_msi_parent_unmask_irq(struct irq_data *data)
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{
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struct imx_mu_msi *msi_data = irq_data_get_irq_chip_data(data);
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imx_mu_xcr_rmw(msi_data, IMX_MU_RCR, IMX_MU_xCR_RIEn(msi_data, data->hwirq), 0);
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}
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static void imx_mu_msi_parent_ack_irq(struct irq_data *data)
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{
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struct imx_mu_msi *msi_data = irq_data_get_irq_chip_data(data);
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imx_mu_read(msi_data, msi_data->cfg->xRR + data->hwirq * 4);
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}
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static struct irq_chip imx_mu_msi_irq_chip = {
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.name = "MU-MSI",
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.irq_ack = irq_chip_ack_parent,
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};
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static struct msi_domain_ops imx_mu_msi_irq_ops = {
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};
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static struct msi_domain_info imx_mu_msi_domain_info = {
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.flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS),
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.ops = &imx_mu_msi_irq_ops,
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.chip = &imx_mu_msi_irq_chip,
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};
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static void imx_mu_msi_parent_compose_msg(struct irq_data *data,
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struct msi_msg *msg)
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{
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struct imx_mu_msi *msi_data = irq_data_get_irq_chip_data(data);
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u64 addr = msi_data->msiir_addr + 4 * data->hwirq;
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msg->address_hi = upper_32_bits(addr);
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msg->address_lo = lower_32_bits(addr);
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msg->data = data->hwirq;
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}
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static int imx_mu_msi_parent_set_affinity(struct irq_data *irq_data,
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const struct cpumask *mask, bool force)
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{
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return -EINVAL;
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}
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static struct irq_chip imx_mu_msi_parent_chip = {
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.name = "MU",
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.irq_mask = imx_mu_msi_parent_mask_irq,
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.irq_unmask = imx_mu_msi_parent_unmask_irq,
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.irq_ack = imx_mu_msi_parent_ack_irq,
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.irq_compose_msi_msg = imx_mu_msi_parent_compose_msg,
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.irq_set_affinity = imx_mu_msi_parent_set_affinity,
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};
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static int imx_mu_msi_domain_irq_alloc(struct irq_domain *domain,
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unsigned int virq,
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unsigned int nr_irqs,
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void *args)
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{
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struct imx_mu_msi *msi_data = domain->host_data;
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unsigned long flags;
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int pos, err = 0;
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WARN_ON(nr_irqs != 1);
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raw_spin_lock_irqsave(&msi_data->lock, flags);
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pos = find_first_zero_bit(&msi_data->used, IMX_MU_CHANS);
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if (pos < IMX_MU_CHANS)
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__set_bit(pos, &msi_data->used);
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else
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err = -ENOSPC;
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raw_spin_unlock_irqrestore(&msi_data->lock, flags);
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if (err)
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return err;
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irq_domain_set_info(domain, virq, pos,
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&imx_mu_msi_parent_chip, msi_data,
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handle_edge_irq, NULL, NULL);
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return 0;
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}
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static void imx_mu_msi_domain_irq_free(struct irq_domain *domain,
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unsigned int virq, unsigned int nr_irqs)
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{
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struct irq_data *d = irq_domain_get_irq_data(domain, virq);
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struct imx_mu_msi *msi_data = irq_data_get_irq_chip_data(d);
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unsigned long flags;
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raw_spin_lock_irqsave(&msi_data->lock, flags);
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__clear_bit(d->hwirq, &msi_data->used);
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raw_spin_unlock_irqrestore(&msi_data->lock, flags);
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}
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static const struct irq_domain_ops imx_mu_msi_domain_ops = {
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.alloc = imx_mu_msi_domain_irq_alloc,
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.free = imx_mu_msi_domain_irq_free,
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};
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static void imx_mu_msi_irq_handler(struct irq_desc *desc)
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{
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struct imx_mu_msi *msi_data = irq_desc_get_handler_data(desc);
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struct irq_chip *chip = irq_desc_get_chip(desc);
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u32 status;
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int i;
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status = imx_mu_read(msi_data, msi_data->cfg->xSR[IMX_MU_RSR]);
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chained_irq_enter(chip, desc);
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for (i = 0; i < IMX_MU_CHANS; i++) {
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if (status & IMX_MU_xSR_RFn(msi_data, i))
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generic_handle_domain_irq(msi_data->msi_domain, i);
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}
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chained_irq_exit(chip, desc);
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}
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static int imx_mu_msi_domains_init(struct imx_mu_msi *msi_data, struct device *dev)
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{
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struct fwnode_handle *fwnodes = dev_fwnode(dev);
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struct irq_domain *parent;
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/* Initialize MSI domain parent */
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parent = irq_domain_create_linear(fwnodes,
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IMX_MU_CHANS,
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&imx_mu_msi_domain_ops,
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msi_data);
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if (!parent) {
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dev_err(dev, "failed to create IRQ domain\n");
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return -ENOMEM;
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}
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irq_domain_update_bus_token(parent, DOMAIN_BUS_NEXUS);
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msi_data->msi_domain = platform_msi_create_irq_domain(fwnodes,
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&imx_mu_msi_domain_info,
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parent);
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if (!msi_data->msi_domain) {
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dev_err(dev, "failed to create MSI domain\n");
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irq_domain_remove(parent);
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return -ENOMEM;
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}
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irq_domain_set_pm_device(msi_data->msi_domain, dev);
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return 0;
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}
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/* Register offset of different version MU IP */
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static const struct imx_mu_dcfg imx_mu_cfg_imx6sx = {
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.type = 0,
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.xTR = 0x0,
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.xRR = 0x10,
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.xSR = {
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[IMX_MU_SR] = 0x20,
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[IMX_MU_GSR] = 0x20,
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[IMX_MU_TSR] = 0x20,
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[IMX_MU_RSR] = 0x20,
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},
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.xCR = {
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[IMX_MU_GIER] = 0x24,
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[IMX_MU_GCR] = 0x24,
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[IMX_MU_TCR] = 0x24,
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[IMX_MU_RCR] = 0x24,
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},
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};
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static const struct imx_mu_dcfg imx_mu_cfg_imx7ulp = {
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.type = 0,
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.xTR = 0x20,
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.xRR = 0x40,
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.xSR = {
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[IMX_MU_SR] = 0x60,
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[IMX_MU_GSR] = 0x60,
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[IMX_MU_TSR] = 0x60,
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[IMX_MU_RSR] = 0x60,
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},
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.xCR = {
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[IMX_MU_GIER] = 0x64,
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[IMX_MU_GCR] = 0x64,
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[IMX_MU_TCR] = 0x64,
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[IMX_MU_RCR] = 0x64,
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},
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};
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static const struct imx_mu_dcfg imx_mu_cfg_imx8ulp = {
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.type = IMX_MU_V2,
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.xTR = 0x200,
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.xRR = 0x280,
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.xSR = {
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[IMX_MU_SR] = 0xC,
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[IMX_MU_GSR] = 0x118,
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[IMX_MU_GSR] = 0x124,
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[IMX_MU_RSR] = 0x12C,
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},
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.xCR = {
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[IMX_MU_GIER] = 0x110,
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[IMX_MU_GCR] = 0x114,
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[IMX_MU_TCR] = 0x120,
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[IMX_MU_RCR] = 0x128
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},
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};
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static int __init imx_mu_of_init(struct device_node *dn,
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struct device_node *parent,
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const struct imx_mu_dcfg *cfg)
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{
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struct platform_device *pdev = of_find_device_by_node(dn);
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struct device_link *pd_link_a;
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struct device_link *pd_link_b;
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struct imx_mu_msi *msi_data;
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struct resource *res;
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struct device *pd_a;
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struct device *pd_b;
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struct device *dev;
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int ret;
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int irq;
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dev = &pdev->dev;
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msi_data = devm_kzalloc(&pdev->dev, sizeof(*msi_data), GFP_KERNEL);
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if (!msi_data)
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return -ENOMEM;
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msi_data->cfg = cfg;
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msi_data->regs = devm_platform_ioremap_resource_byname(pdev, "processor-a-side");
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if (IS_ERR(msi_data->regs)) {
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dev_err(&pdev->dev, "failed to initialize 'regs'\n");
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return PTR_ERR(msi_data->regs);
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}
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "processor-b-side");
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if (!res)
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return -EIO;
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msi_data->msiir_addr = res->start + msi_data->cfg->xTR;
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irq = platform_get_irq(pdev, 0);
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if (irq <= 0)
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return -ENODEV;
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platform_set_drvdata(pdev, msi_data);
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msi_data->clk = devm_clk_get(dev, NULL);
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if (IS_ERR(msi_data->clk))
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return PTR_ERR(msi_data->clk);
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pd_a = dev_pm_domain_attach_by_name(dev, "processor-a-side");
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if (IS_ERR(pd_a))
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return PTR_ERR(pd_a);
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pd_b = dev_pm_domain_attach_by_name(dev, "processor-b-side");
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if (IS_ERR(pd_b))
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return PTR_ERR(pd_b);
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pd_link_a = device_link_add(dev, pd_a,
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DL_FLAG_STATELESS |
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DL_FLAG_PM_RUNTIME |
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DL_FLAG_RPM_ACTIVE);
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if (!pd_link_a) {
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dev_err(dev, "Failed to add device_link to mu a.\n");
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goto err_pd_a;
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}
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pd_link_b = device_link_add(dev, pd_b,
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DL_FLAG_STATELESS |
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DL_FLAG_PM_RUNTIME |
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DL_FLAG_RPM_ACTIVE);
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if (!pd_link_b) {
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dev_err(dev, "Failed to add device_link to mu a.\n");
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goto err_pd_b;
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}
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ret = imx_mu_msi_domains_init(msi_data, dev);
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if (ret)
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goto err_dm_init;
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pm_runtime_enable(dev);
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irq_set_chained_handler_and_data(irq,
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imx_mu_msi_irq_handler,
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msi_data);
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return 0;
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err_dm_init:
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device_link_remove(dev, pd_b);
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err_pd_b:
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device_link_remove(dev, pd_a);
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err_pd_a:
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return -EINVAL;
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}
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static int __maybe_unused imx_mu_runtime_suspend(struct device *dev)
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{
|
||||
struct imx_mu_msi *priv = dev_get_drvdata(dev);
|
||||
|
||||
clk_disable_unprepare(priv->clk);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int __maybe_unused imx_mu_runtime_resume(struct device *dev)
|
||||
{
|
||||
struct imx_mu_msi *priv = dev_get_drvdata(dev);
|
||||
int ret;
|
||||
|
||||
ret = clk_prepare_enable(priv->clk);
|
||||
if (ret)
|
||||
dev_err(dev, "failed to enable clock\n");
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static const struct dev_pm_ops imx_mu_pm_ops = {
|
||||
SET_RUNTIME_PM_OPS(imx_mu_runtime_suspend,
|
||||
imx_mu_runtime_resume, NULL)
|
||||
};
|
||||
|
||||
static int __init imx_mu_imx7ulp_of_init(struct device_node *dn,
|
||||
struct device_node *parent)
|
||||
{
|
||||
return imx_mu_of_init(dn, parent, &imx_mu_cfg_imx7ulp);
|
||||
}
|
||||
|
||||
static int __init imx_mu_imx6sx_of_init(struct device_node *dn,
|
||||
struct device_node *parent)
|
||||
{
|
||||
return imx_mu_of_init(dn, parent, &imx_mu_cfg_imx6sx);
|
||||
}
|
||||
|
||||
static int __init imx_mu_imx8ulp_of_init(struct device_node *dn,
|
||||
struct device_node *parent)
|
||||
{
|
||||
return imx_mu_of_init(dn, parent, &imx_mu_cfg_imx8ulp);
|
||||
}
|
||||
|
||||
IRQCHIP_PLATFORM_DRIVER_BEGIN(imx_mu_msi)
|
||||
IRQCHIP_MATCH("fsl,imx7ulp-mu-msi", imx_mu_imx7ulp_of_init)
|
||||
IRQCHIP_MATCH("fsl,imx6sx-mu-msi", imx_mu_imx6sx_of_init)
|
||||
IRQCHIP_MATCH("fsl,imx8ulp-mu-msi", imx_mu_imx8ulp_of_init)
|
||||
IRQCHIP_PLATFORM_DRIVER_END(imx_mu_msi, .pm = &imx_mu_pm_ops)
|
||||
|
||||
|
||||
MODULE_AUTHOR("Frank Li <Frank.Li@nxp.com>");
|
||||
MODULE_DESCRIPTION("Freescale MU MSI controller driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
Loading…
Reference in New Issue