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x86/apic: Fix use of X{,2}APIC_ENABLE in asm with older binutils 

"x86/smpboot: Support parallel startup of secondary CPUs" adds the first use
of X2APIC_ENABLE in assembly, but older binutils don't tolerate the UL suffix.

Switch to using BIT() instead.

Fixes: 7e75178a09 ("x86/smpboot: Support parallel startup of secondary CPUs")
Reported-by: Jeffrey Hugo <quic_jhugo@quicinc.com>
Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Tested-by: Jeffrey Hugo <quic_jhugo@quicinc.com>
Link: https://lore.kernel.org/r/20230522105738.2378364-1-andrew.cooper3@citrix.com
This commit is contained in:
Andrew Cooper 2023-05-22 11:57:38 +01:00 committed by Thomas Gleixner
parent 0c7ffa32db
commit 6a4be69845
1 changed files with 4 additions and 2 deletions
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6
arch/x86/include/asm/apicdef.h
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@ -2,6 +2,8 @@
#ifndef _ASM_X86_APICDEF_H #ifndef _ASM_X86_APICDEF_H
#define _ASM_X86_APICDEF_H #define _ASM_X86_APICDEF_H
#include <linux/bits.h>
/* /*
* Constants for various Intel APICs. (local APIC, IOAPIC, etc.) * Constants for various Intel APICs. (local APIC, IOAPIC, etc.)
* *
@ -140,8 +142,8 @@
#define APIC_BASE (fix_to_virt(FIX_APIC_BASE)) #define APIC_BASE (fix_to_virt(FIX_APIC_BASE))
#define APIC_BASE_MSR 0x800 #define APIC_BASE_MSR 0x800
#define APIC_X2APIC_ID_MSR 0x802 #define APIC_X2APIC_ID_MSR 0x802
#define XAPIC_ENABLE (1UL << 11) #define XAPIC_ENABLE BIT(11)
#define X2APIC_ENABLE (1UL << 10) #define X2APIC_ENABLE BIT(10)
#ifdef CONFIG_X86_32 #ifdef CONFIG_X86_32
# define MAX_IO_APICS 64 # define MAX_IO_APICS 64