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arm64: tegra: Mark BPMP channels as no-memory-wc 

The Tegra SYSRAM contains regions access to which is restricted to
certain hardware blocks on the system, and speculative accesses to
those will cause issues.

Patch 'misc: sram: Only map reserved areas in Tegra SYSRAM' attempted
to resolve this by only mapping the regions specified in the device
tree on the assumption that there are no such restricted areas within
the 64K-aligned area of memory that contains the memory we wish to map.

Turns out this assumption is wrong, as there are such areas above the
4K pages described in the device trees. As such, we need to use the
bigger hammer that is no-memory-wc, which causes the memory to be
mapped as Device memory to which speculative accesses are disallowed.

As such, the previous patch in the series,
  'firmware: tegra: bpmp: do only aligned access to IPC memory area',
is required with this patch to make the BPMP driver only issue aligned
memory accesses as those are also required with Device memory.

Fixes: fec29bf049 ("misc: sram: Only map reserved areas in Tegra SYSRAM")
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Reviewed-by: Yousaf Kaukab <ykaukab@suse.de>
Signed-off-by: Thierry Reding <treding@nvidia.com>
This commit is contained in:
Mikko Perttunen 2022-06-22 16:23:00 +03:00 committed by Thierry Reding
parent 60d2016a51
commit 61192a9d8a
3 changed files with 3 additions and 0 deletions
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1
arch/arm64/boot/dts/nvidia/tegra186.dtsi
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@ -1843,6 +1843,7 @@ sram@30000000 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
ranges = <0x0 0x0 0x30000000 0x50000>; ranges = <0x0 0x0 0x30000000 0x50000>;
no-memory-wc;
cpu_bpmp_tx: sram@4e000 { cpu_bpmp_tx: sram@4e000 {
reg = <0x4e000 0x1000>; reg = <0x4e000 0x1000>;

1
arch/arm64/boot/dts/nvidia/tegra194.dtsi
View File

@ -2707,6 +2707,7 @@ sram@40000000 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
ranges = <0x0 0x0 0x40000000 0x50000>; ranges = <0x0 0x0 0x40000000 0x50000>;
no-memory-wc;
cpu_bpmp_tx: sram@4e000 { cpu_bpmp_tx: sram@4e000 {
reg = <0x4e000 0x1000>; reg = <0x4e000 0x1000>;

1
arch/arm64/boot/dts/nvidia/tegra234.dtsi
View File

@ -1390,6 +1390,7 @@ sram@40000000 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
ranges = <0x0 0x0 0x40000000 0x80000>; ranges = <0x0 0x0 0x40000000 0x80000>;
no-memory-wc;
cpu_bpmp_tx: sram@70000 { cpu_bpmp_tx: sram@70000 {
reg = <0x70000 0x1000>; reg = <0x70000 0x1000>;