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drm/i915: mark requests for GuC virtual engines to avoid use-after-free 

References to i915_requests may be trapped by userspace inside a
sync_file or dmabuf (dma-resv) and held indefinitely across different
proceses. To counter-act the memory leaks, we try to not to keep
references from the request past their completion.
On the other side on fence release we need to know if rq->engine
is valid and points to hw engine (true for non-virtual requests).
To make it possible extra bit has been added to rq->execution_mask,
for marking virtual engines.

Fixes: bcb9aa45d5 ("Revert "drm/i915: Hold reference to intel_context over life of i915_request"")
Signed-off-by: Chris Wilson <chris.p.wilson@linux.intel.com>
Signed-off-by: Andrzej Hajda <andrzej.hajda@intel.com>
Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com>
Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230821153035.3903006-1-andrzej.hajda@intel.com
(cherry picked from commit 280410677af763f3871b93e794a199cfcf6fb580)
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
This commit is contained in:
Andrzej Hajda 2023-08-21 17:30:35 +02:00 committed by Rodrigo Vivi
parent 3698a75f5a
commit 5eefc5307c
3 changed files with 6 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
drivers/gpu/drm/i915/gt/intel_engine_types.h
View File

@ -58,6 +58,7 @@ struct i915_perf_group;
typedef u32 intel_engine_mask_t; typedef u32 intel_engine_mask_t;
#define ALL_ENGINES ((intel_engine_mask_t)~0ul) #define ALL_ENGINES ((intel_engine_mask_t)~0ul)
#define VIRTUAL_ENGINES BIT(BITS_PER_TYPE(intel_engine_mask_t) - 1)
struct intel_hw_status_page { struct intel_hw_status_page {
struct list_head timelines; struct list_head timelines;

3
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
View File

@ -5470,6 +5470,9 @@ guc_create_virtual(struct intel_engine_cs **siblings, unsigned int count,
ve->base.flags = I915_ENGINE_IS_VIRTUAL; ve->base.flags = I915_ENGINE_IS_VIRTUAL;
BUILD_BUG_ON(ilog2(VIRTUAL_ENGINES) < I915_NUM_ENGINES);
ve->base.mask = VIRTUAL_ENGINES;
intel_context_init(&ve->context, &ve->base); intel_context_init(&ve->context, &ve->base);
for (n = 0; n < count; n++) { for (n = 0; n < count; n++) {

7
drivers/gpu/drm/i915/i915_request.c
View File

@ -134,9 +134,7 @@ static void i915_fence_release(struct dma_fence *fence)
i915_sw_fence_fini(&rq->semaphore); i915_sw_fence_fini(&rq->semaphore);
/* /*
* Keep one request on each engine for reserved use under mempressure * Keep one request on each engine for reserved use under mempressure.
* do not use with virtual engines as this really is only needed for
* kernel contexts.
* *
* We do not hold a reference to the engine here and so have to be * We do not hold a reference to the engine here and so have to be
* very careful in what rq->engine we poke. The virtual engine is * very careful in what rq->engine we poke. The virtual engine is
@ -166,8 +164,7 @@ static void i915_fence_release(struct dma_fence *fence)
* know that if the rq->execution_mask is a single bit, rq->engine * know that if the rq->execution_mask is a single bit, rq->engine
* can be a physical engine with the exact corresponding mask. * can be a physical engine with the exact corresponding mask.
*/ */
if (!intel_engine_is_virtual(rq->engine) && if (is_power_of_2(rq->execution_mask) &&
is_power_of_2(rq->execution_mask) &&
!cmpxchg(&rq->engine->request_pool, NULL, rq)) !cmpxchg(&rq->engine->request_pool, NULL, rq))
return; return;