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xtensa: PMU: fix base address for the newer hardware 

commit 687eb3c42f upstream.

With introduction of ERI access control in RG.0 base address of the PMU
unit registers has changed. Add support for the new PMU configuration.

Cc: stable@vger.kernel.org
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Max Filippov 2023-07-24 00:58:24 -07:00 committed by Greg Kroah-Hartman
parent 9a9b8596c3
commit 5a8b2c1665
2 changed files with 22 additions and 4 deletions
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9
arch/xtensa/include/asm/core.h
View File

@ -44,4 +44,13 @@
#define XTENSA_STACK_ALIGNMENT 16 #define XTENSA_STACK_ALIGNMENT 16
#endif #endif
#ifndef XCHAL_HW_MIN_VERSION
#if defined(XCHAL_HW_MIN_VERSION_MAJOR) && defined(XCHAL_HW_MIN_VERSION_MINOR)
#define XCHAL_HW_MIN_VERSION (XCHAL_HW_MIN_VERSION_MAJOR * 100 + \
XCHAL_HW_MIN_VERSION_MINOR)
#else
#define XCHAL_HW_MIN_VERSION 0
#endif
#endif
#endif #endif

17
arch/xtensa/kernel/perf_event.c
View File

@ -13,17 +13,26 @@
#include <linux/perf_event.h> #include <linux/perf_event.h>
#include <linux/platform_device.h> #include <linux/platform_device.h>
#include <asm/core.h>
#include <asm/processor.h> #include <asm/processor.h>
#include <asm/stacktrace.h> #include <asm/stacktrace.h>
#define XTENSA_HWVERSION_RG_2015_0 260000
#if XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RG_2015_0
#define XTENSA_PMU_ERI_BASE 0x00101000
#else
#define XTENSA_PMU_ERI_BASE 0x00001000
#endif
/* Global control/status for all perf counters */ /* Global control/status for all perf counters */
#define XTENSA_PMU_PMG 0x1000 #define XTENSA_PMU_PMG XTENSA_PMU_ERI_BASE
/* Perf counter values */ /* Perf counter values */
#define XTENSA_PMU_PM(i) (0x1080 + (i) * 4) #define XTENSA_PMU_PM(i) (XTENSA_PMU_ERI_BASE + 0x80 + (i) * 4)
/* Perf counter control registers */ /* Perf counter control registers */
#define XTENSA_PMU_PMCTRL(i) (0x1100 + (i) * 4) #define XTENSA_PMU_PMCTRL(i) (XTENSA_PMU_ERI_BASE + 0x100 + (i) * 4)
/* Perf counter status registers */ /* Perf counter status registers */
#define XTENSA_PMU_PMSTAT(i) (0x1180 + (i) * 4) #define XTENSA_PMU_PMSTAT(i) (XTENSA_PMU_ERI_BASE + 0x180 + (i) * 4)
#define XTENSA_PMU_PMG_PMEN 0x1 #define XTENSA_PMU_PMG_PMEN 0x1