dt-bindings: mfd: Convert stm32 timers bindings to json-schema
Convert the STM32 timers binding to DT schema format using json-schema Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com> Signed-off-by: Rob Herring <robh@kernel.org>
This commit is contained in:
Benjamin Gaignard
Rob Herring
parent
93512dad33
commit
56fb34d86e
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STMicroelectronics STM32 Timer quadrature encoder
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STM32 Timer provides quadrature encoder to detect
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angular position and direction of rotary elements,
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from IN1 and IN2 input signals.
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Must be a sub-node of an STM32 Timer device tree node.
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See ../mfd/stm32-timers.txt for details about the parent node.
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Required properties:
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- compatible: Must be "st,stm32-timer-counter".
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- pinctrl-names: Set to "default".
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- pinctrl-0: List of phandles pointing to pin configuration nodes,
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to set CH1/CH2 pins in mode of operation for STM32
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Timer input on external pin.
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Example:
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timers@40010000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "st,stm32-timers";
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reg = <0x40010000 0x400>;
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clocks = <&rcc 0 160>;
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clock-names = "int";
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counter {
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compatible = "st,stm32-timer-counter";
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pinctrl-names = "default";
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pinctrl-0 = <&tim1_in_pins>;
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};
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};
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STMicroelectronics STM32 Timers IIO timer bindings
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Must be a sub-node of an STM32 Timers device tree node.
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See ../mfd/stm32-timers.txt for details about the parent node.
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Required parameters:
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- compatible: Must be one of:
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"st,stm32-timer-trigger"
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"st,stm32h7-timer-trigger"
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- reg: Identify trigger hardware block.
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Example:
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timers@40010000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "st,stm32-timers";
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reg = <0x40010000 0x400>;
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clocks = <&rcc 0 160>;
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clock-names = "int";
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timer@0 {
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compatible = "st,stm32-timer-trigger";
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reg = <0>;
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};
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};
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/mfd/st,stm32-timers.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: STMicroelectronics STM32 Timers bindings
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description: |
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This hardware block provides 3 types of timer along with PWM functionality:
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- advanced-control timers consist of a 16-bit auto-reload counter driven
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by a programmable prescaler, break input feature, PWM outputs and
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complementary PWM outputs channels.
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- general-purpose timers consist of a 16-bit or 32-bit auto-reload counter
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driven by a programmable prescaler and PWM outputs.
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- basic timers consist of a 16-bit auto-reload counter driven by a
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programmable prescaler.
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maintainers:
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- Benjamin Gaignard <benjamin.gaignard@st.com>
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- Fabrice Gasnier <fabrice.gasnier@st.com>
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properties:
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compatible:
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const: st,stm32-timers
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reg:
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maxItems: 1
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clocks:
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maxItems: 1
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clock-names:
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items:
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- const: int
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reset:
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maxItems: 1
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dmas:
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minItems: 1
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maxItems: 7
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dma-names:
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items:
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enum: [ ch1, ch2, ch3, ch4, up, trig, com ]
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minItems: 1
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maxItems: 7
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"#address-cells":
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const: 1
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"#size-cells":
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const: 0
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pwm:
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type: object
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properties:
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compatible:
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const: st,stm32-pwm
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"#pwm-cells":
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const: 3
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st,breakinput:
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description:
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One or two <index level filter> to describe break input
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configurations.
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allOf:
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- $ref: /schemas/types.yaml#/definitions/uint32-matrix
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- items:
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items:
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- description: |
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"index" indicates on which break input (0 or 1) the
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configuration should be applied.
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enum: [ 0 , 1]
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- description: |
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"level" gives the active level (0=low or 1=high) of the
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input signal for this configuration
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enum: [ 0, 1 ]
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- description: |
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"filter" gives the filtering value (up to 15) to be applied.
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maximum: 15
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minItems: 1
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maxItems: 2
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required:
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- "#pwm-cells"
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- compatible
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patternProperties:
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"^timer@[0-9]+$":
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type: object
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properties:
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compatible:
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enum:
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- st,stm32-timer-trigger
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- st,stm32h7-timer-trigger
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reg:
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description: Identify trigger hardware block.
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items:
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minimum: 0
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maximum: 16
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required:
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- compatible
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- reg
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counter:
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type: object
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properties:
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compatible:
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const: st,stm32-timer-counter
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required:
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- compatible
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required:
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- "#address-cells"
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- "#size-cells"
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- compatible
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- reg
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- clocks
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- clock-names
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/stm32mp1-clks.h>
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timers2: timers@40000000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "st,stm32-timers";
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reg = <0x40000000 0x400>;
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clocks = <&rcc TIM2_K>;
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clock-names = "int";
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dmas = <&dmamux1 18 0x400 0x1>,
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<&dmamux1 19 0x400 0x1>,
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<&dmamux1 20 0x400 0x1>,
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<&dmamux1 21 0x400 0x1>,
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<&dmamux1 22 0x400 0x1>;
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dma-names = "ch1", "ch2", "ch3", "ch4", "up";
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pwm {
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compatible = "st,stm32-pwm";
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#pwm-cells = <3>;
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st,breakinput = <0 1 5>;
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};
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timer@0 {
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compatible = "st,stm32-timer-trigger";
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reg = <0>;
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};
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counter {
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compatible = "st,stm32-timer-counter";
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};
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};
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...
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@ -1,73 +0,0 @@
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STM32 Timers driver bindings
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This IP provides 3 types of timer along with PWM functionality:
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- advanced-control timers consist of a 16-bit auto-reload counter driven by a programmable
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prescaler, break input feature, PWM outputs and complementary PWM ouputs channels.
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- general-purpose timers consist of a 16-bit or 32-bit auto-reload counter driven by a
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programmable prescaler and PWM outputs.
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- basic timers consist of a 16-bit auto-reload counter driven by a programmable prescaler.
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Required parameters:
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- compatible: must be "st,stm32-timers"
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- reg: Physical base address and length of the controller's
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registers.
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- clock-names: Set to "int".
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- clocks: Phandle to the clock used by the timer module.
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For Clk properties, please refer to ../clock/clock-bindings.txt
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Optional parameters:
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- resets: Phandle to the parent reset controller.
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See ../reset/st,stm32-rcc.txt
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- dmas: List of phandle to dma channels that can be used for
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this timer instance. There may be up to 7 dma channels.
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- dma-names: List of dma names. Must match 'dmas' property. Valid
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names are: "ch1", "ch2", "ch3", "ch4", "up", "trig",
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"com".
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Optional subnodes:
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- pwm: See ../pwm/pwm-stm32.txt
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- timer: See ../iio/timer/stm32-timer-trigger.txt
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- counter: See ../counter/stm32-timer-cnt.txt
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Example:
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timers@40010000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "st,stm32-timers";
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reg = <0x40010000 0x400>;
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clocks = <&rcc 0 160>;
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clock-names = "int";
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pwm {
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compatible = "st,stm32-pwm";
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pinctrl-0 = <&pwm1_pins>;
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pinctrl-names = "default";
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};
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timer@0 {
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compatible = "st,stm32-timer-trigger";
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reg = <0>;
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};
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counter {
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compatible = "st,stm32-timer-counter";
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pinctrl-names = "default";
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pinctrl-0 = <&tim1_in_pins>;
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};
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};
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Example with all dmas:
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timer@40010000 {
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...
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dmas = <&dmamux1 11 0x400 0x0>,
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<&dmamux1 12 0x400 0x0>,
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<&dmamux1 13 0x400 0x0>,
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<&dmamux1 14 0x400 0x0>,
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<&dmamux1 15 0x400 0x0>,
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<&dmamux1 16 0x400 0x0>,
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<&dmamux1 17 0x400 0x0>;
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dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig", "com";
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...
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child nodes...
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};
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@ -1,38 +0,0 @@
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STMicroelectronics STM32 Timers PWM bindings
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Must be a sub-node of an STM32 Timers device tree node.
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See ../mfd/stm32-timers.txt for details about the parent node.
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Required parameters:
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- compatible: Must be "st,stm32-pwm".
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- pinctrl-names: Set to "default".
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- pinctrl-0: List of phandles pointing to pin configuration nodes for PWM module.
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For Pinctrl properties see ../pinctrl/pinctrl-bindings.txt
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- #pwm-cells: Should be set to 3. This PWM chip uses the default 3 cells
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bindings defined in pwm.txt.
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Optional parameters:
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- st,breakinput: One or two <index level filter> to describe break input configurations.
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"index" indicates on which break input (0 or 1) the configuration
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should be applied.
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"level" gives the active level (0=low or 1=high) of the input signal
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for this configuration.
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"filter" gives the filtering value to be applied.
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Example:
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timers@40010000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "st,stm32-timers";
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reg = <0x40010000 0x400>;
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clocks = <&rcc 0 160>;
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clock-names = "int";
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pwm {
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compatible = "st,stm32-pwm";
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#pwm-cells = <3>;
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pinctrl-0 = <&pwm1_pins>;
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pinctrl-names = "default";
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st,breakinput = <0 1 5>;
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};
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};
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