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arm64: dts: uniphier: Add L2 cache node 

Add a L2 cache node referenced from CPU nodes as the missing cache hierarchy
information because the following warning was issued.

  cacheinfo: Unable to detect cache hierarchy for CPU 0
  Early cacheinfo failed, ret = -2

Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Link: https://lore.kernel.org/r/20220913042321.4817-11-hayashi.kunihiko@socionext.com'
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Kunihiko Hayashi 2022-09-13 13:23:21 +09:00 committed by Arnd Bergmann
parent d93ecbf569
commit 5381a96cd9
No known key found for this signature in database
GPG Key ID: 9A6C79EFE60018D9
3 changed files with 26 additions and 0 deletions
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6
arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi
View File

@ -36,6 +36,7 @@ cpu0: cpu@0 {
reg = <0 0x000>;
clocks = <&sys_clk 33>;
enable-method = "psci";
next-level-cache = <&l2>;
operating-points-v2 = <&cluster0_opp>;
};
@ -45,8 +46,13 @@ cpu1: cpu@1 {
reg = <0 0x001>;
clocks = <&sys_clk 33>;
enable-method = "psci";
next-level-cache = <&l2>;
operating-points-v2 = <&cluster0_opp>;
};
l2: l2-cache {
compatible = "cache";
};
};
cluster0_opp: opp-table {

12
arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
View File

@ -46,6 +46,7 @@ cpu0: cpu@0 {
reg = <0 0x000>;
clocks = <&sys_clk 32>;
enable-method = "psci";
next-level-cache = <&a72_l2>;
operating-points-v2 = <&cluster0_opp>;
#cooling-cells = <2>;
};
@ -56,6 +57,7 @@ cpu1: cpu@1 {
reg = <0 0x001>;
clocks = <&sys_clk 32>;
enable-method = "psci";
next-level-cache = <&a72_l2>;
operating-points-v2 = <&cluster0_opp>;
#cooling-cells = <2>;
};
@ -66,6 +68,7 @@ cpu2: cpu@100 {
reg = <0 0x100>;
clocks = <&sys_clk 33>;
enable-method = "psci";
next-level-cache = <&a53_l2>;
operating-points-v2 = <&cluster1_opp>;
#cooling-cells = <2>;
};
@ -76,9 +79,18 @@ cpu3: cpu@101 {
reg = <0 0x101>;
clocks = <&sys_clk 33>;
enable-method = "psci";
next-level-cache = <&a53_l2>;
operating-points-v2 = <&cluster1_opp>;
#cooling-cells = <2>;
};
a72_l2: l2-cache0 {
compatible = "cache";
};
a53_l2: l2-cache1 {
compatible = "cache";
};
};
cluster0_opp: opp-table-0 {

8
arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi
View File

@ -43,6 +43,7 @@ cpu0: cpu@0 {
reg = <0 0x000>;
clocks = <&sys_clk 33>;
enable-method = "psci";
next-level-cache = <&l2>;
operating-points-v2 = <&cluster0_opp>;
#cooling-cells = <2>;
};
@ -53,6 +54,7 @@ cpu1: cpu@1 {
reg = <0 0x001>;
clocks = <&sys_clk 33>;
enable-method = "psci";
next-level-cache = <&l2>;
operating-points-v2 = <&cluster0_opp>;
#cooling-cells = <2>;
};
@ -63,6 +65,7 @@ cpu2: cpu@2 {
reg = <0 0x002>;
clocks = <&sys_clk 33>;
enable-method = "psci";
next-level-cache = <&l2>;
operating-points-v2 = <&cluster0_opp>;
#cooling-cells = <2>;
};
@ -73,9 +76,14 @@ cpu3: cpu@3 {
reg = <0 0x003>;
clocks = <&sys_clk 33>;
enable-method = "psci";
next-level-cache = <&l2>;
operating-points-v2 = <&cluster0_opp>;
#cooling-cells = <2>;
};
l2: l2-cache {
compatible = "cache";
};
};
cluster0_opp: opp-table {