dt-bindings: ufs: hisilicon,ufs: convert to dtschema
Convert the HiSilicon Universal Flash Storage (UFS) Controller to DT schema format. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220306111125.116455-7-krzysztof.kozlowski@canonical.com
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Krzysztof Kozlowski
Rob Herring
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462c5c0aa7
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/ufs/hisilicon,ufs.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: HiSilicon Universal Flash Storage (UFS) Controller
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maintainers:
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- Li Wei <liwei213@huawei.com>
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# Select only our matches, not all jedec,ufs
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select:
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properties:
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compatible:
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contains:
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enum:
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- hisilicon,hi3660-ufs
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- hisilicon,hi3670-ufs
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required:
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- compatible
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allOf:
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- $ref: ufs-common.yaml
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properties:
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compatible:
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oneOf:
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- items:
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- const: hisilicon,hi3660-ufs
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- const: jedec,ufs-1.1
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- items:
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- enum:
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- hisilicon,hi3670-ufs
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- const: jedec,ufs-2.1
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clocks:
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minItems: 2
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maxItems: 2
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clock-names:
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items:
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- const: ref_clk
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- const: phy_clk
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reg:
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items:
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- description: UFS register address space
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- description: UFS SYS CTRL register address space
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resets:
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maxItems: 1
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reset-names:
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items:
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- const: rst
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required:
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- compatible
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- reg
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- resets
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- reset-names
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/hi3670-clock.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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ufs@ff3c0000 {
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compatible = "hisilicon,hi3670-ufs", "jedec,ufs-2.1";
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reg = <0x0 0xff3c0000 0x0 0x1000>,
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<0x0 0xff3e0000 0x0 0x1000>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&crg_ctrl HI3670_CLK_GATE_UFSIO_REF>,
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<&crg_ctrl HI3670_CLK_GATE_UFS_SUBSYS>;
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clock-names = "ref_clk", "phy_clk";
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freq-table-hz = <0 0>,
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<0 0>;
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resets = <&crg_rst 0x84 12>;
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reset-names = "rst";
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};
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};
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@ -1,42 +0,0 @@
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* Hisilicon Universal Flash Storage (UFS) Host Controller
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UFS nodes are defined to describe on-chip UFS hardware macro.
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Each UFS Host Controller should have its own node.
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Required properties:
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- compatible : compatible list, contains one of the following -
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"hisilicon,hi3660-ufs", "jedec,ufs-1.1" for hisi ufs
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host controller present on Hi3660 chipset.
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"hisilicon,hi3670-ufs", "jedec,ufs-2.1" for hisi ufs
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host controller present on Hi3670 chipset.
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- reg : should contain UFS register address space & UFS SYS CTRL register address,
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- interrupts : interrupt number
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- clocks : List of phandle and clock specifier pairs
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- clock-names : List of clock input name strings sorted in the same
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order as the clocks property. "ref_clk", "phy_clk" is optional
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- freq-table-hz : Array of <min max> operating frequencies stored in the same
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order as the clocks property. If this property is not
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defined or a value in the array is "0" then it is assumed
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that the frequency is set by the parent clock or a
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fixed rate clock source.
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- resets : describe reset node register
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- reset-names : reset node register, the "rst" corresponds to reset the whole UFS IP.
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Example:
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ufs: ufs@ff3b0000 {
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compatible = "hisilicon,hi3660-ufs", "jedec,ufs-1.1";
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/* 0: HCI standard */
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/* 1: UFS SYS CTRL */
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reg = <0x0 0xff3b0000 0x0 0x1000>,
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<0x0 0xff3b1000 0x0 0x1000>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&crg_ctrl HI3660_CLK_GATE_UFSIO_REF>,
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<&crg_ctrl HI3660_CLK_GATE_UFSPHY_CFG>;
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clock-names = "ref_clk", "phy_clk";
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freq-table-hz = <0 0>, <0 0>;
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/* offset: 0x84; bit: 12 */
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resets = <&crg_rst 0x84 12>;
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reset-names = "rst";
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};
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