iommu/vt-d: Fix to flush cache of PASID directory table
[ Upstream commit8a3b8e63f8
] Even the PCI devices don't support pasid capability, PASID table is mandatory for a PCI device in scalable mode. However flushing cache of pasid directory table for these devices are not taken after pasid table is allocated as the "size" of table is zero. Fix it by calculating the size by page order. Found this when reading the code, no real problem encountered for now. Fixes:194b3348bd
("iommu/vt-d: Fix PASID directory pointer coherency") Suggested-by: Lu Baolu <baolu.lu@linux.intel.com> Signed-off-by: Yanfei Xu <yanfei.xu@intel.com> Link: https://lore.kernel.org/r/20230616081045.721873-1-yanfei.xu@intel.com Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com> Signed-off-by: Joerg Roedel <jroedel@suse.de> Signed-off-by: Sasha Levin <sashal@kernel.org>
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@ -127,7 +127,7 @@ int intel_pasid_alloc_table(struct device *dev)
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info->pasid_table = pasid_table;
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if (!ecap_coherent(info->iommu->ecap))
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clflush_cache_range(pasid_table->table, size);
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clflush_cache_range(pasid_table->table, (1 << order) * PAGE_SIZE);
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return 0;
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}
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