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drm/bridge: Document the expected behaviour of DSI host controllers 

The exact behaviour of DSI host controllers is not specified,
therefore define it.

Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Link: https://lore.kernel.org/r/20221205173328.1395350-7-dave.stevenson@raspberrypi.com
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
This commit is contained in:
Dave Stevenson 2022-12-05 17:33:28 +00:00 committed by Junxiao Chang
parent ed8767c075
commit 454f0bb983
2 changed files with 46 additions and 0 deletions
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7
Documentation/gpu/drm-kms-helpers.rst
View File

@ -185,6 +185,13 @@ Bridge Helper Reference
.. kernel-doc:: drivers/gpu/drm/drm_bridge.c .. kernel-doc:: drivers/gpu/drm/drm_bridge.c
:export: :export:
MIPI-DSI bridge operation
-------------------------
.. kernel-doc:: drivers/gpu/drm/drm_bridge.c
:doc: dsi bridge operations
Bridge Connector Helper Reference Bridge Connector Helper Reference
--------------------------------- ---------------------------------

39
drivers/gpu/drm/drm_bridge.c
View File

@ -153,6 +153,45 @@
* situation when probing. * situation when probing.
*/ */
/**
* DOC: dsi bridge operations
*
* DSI host interfaces are expected to be implemented as bridges rather than
* encoders, however there are a few aspects of their operation that need to
* be defined in order to provide a consistent interface.
*
* A DSI host should keep the PHY powered down until the pre_enable operation is
* called. All lanes are in an undefined idle state up to this point, and it
* must not be assumed that it is LP-11.
* pre_enable should initialise the PHY, set the data lanes to LP-11, and the
* clock lane to either LP-11 or HS depending on the mode_flag
* %MIPI_DSI_CLOCK_NON_CONTINUOUS.
*
* Ordinarily the downstream bridge DSI peripheral pre_enable will have been
* called before the DSI host. If the DSI peripheral requires LP-11 and/or
* the clock lane to be in HS mode prior to pre_enable, then it can set the
* &pre_enable_prev_first flag to request the pre_enable (and
* post_disable) order to be altered to enable the DSI host first.
*
* Either the CRTC being enabled, or the DSI host enable operation should switch
* the host to actively transmitting video on the data lanes.
*
* The reverse also applies. The DSI host disable operation or stopping the CRTC
* should stop transmitting video, and the data lanes should return to the LP-11
* state. The DSI host &post_disable operation should disable the PHY.
* If the &pre_enable_prev_first flag is set, then the DSI peripheral's
* bridge &post_disable will be called before the DSI host's post_disable.
*
* Whilst it is valid to call &host_transfer prior to pre_enable or after
* post_disable, the exact state of the lanes is undefined at this point. The
* DSI host should initialise the interface, transmit the data, and then disable
* the interface again.
*
* Ultra Low Power State (ULPS) is not explicitly supported by DRM. If
* implemented, it therefore needs to be handled entirely within the DSI Host
* driver.
*/
static DEFINE_MUTEX(bridge_lock); static DEFINE_MUTEX(bridge_lock);
static LIST_HEAD(bridge_list); static LIST_HEAD(bridge_list);