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spi: dw: Define the capabilities in a continuous bit-flags set 

Since the DW_SPI_CAP_DWC_HSSI capability has just been replaced with using
the DW SSI IP-core versions interface, the DW SPI capability flags are now
represented with a gap. Let's fix it by redefining the DW_SPI_CAP_DFS32
macro to setting BIT(2) of the capabilities field.

Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Suggested-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Link: https://lore.kernel.org/r/20211115181917.7521-8-Sergey.Semin@baikalelectronics.ru
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Serge Semin 2021-11-15 21:19:17 +03:00 committed by Mark Brown
parent 2b8a47e0b6
commit 44ebcb4458
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GPG Key ID: 24D68B725D5487D0
1 changed files with 1 additions and 1 deletions
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2
drivers/spi/spi-dw.h
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@ -32,7 +32,7 @@
/* DW SPI controller capabilities */ /* DW SPI controller capabilities */
#define DW_SPI_CAP_CS_OVERRIDE BIT(0) #define DW_SPI_CAP_CS_OVERRIDE BIT(0)
#define DW_SPI_CAP_KEEMBAY_MST BIT(1) #define DW_SPI_CAP_KEEMBAY_MST BIT(1)
#define DW_SPI_CAP_DFS32 BIT(3) #define DW_SPI_CAP_DFS32 BIT(2)
/* Register offsets (Generic for both DWC APB SSI and DWC SSI IP-cores) */ /* Register offsets (Generic for both DWC APB SSI and DWC SSI IP-cores) */
#define DW_SPI_CTRLR0 0x00 #define DW_SPI_CTRLR0 0x00