pci-v6.1-fixes-1
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commit
41410965c3
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@ -1768,10 +1768,7 @@ static void adjust_bridge_window(struct pci_dev *bridge, struct resource *res,
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}
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res->end = res->start + new_size - 1;
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/* If the resource is part of the add_list remove it now */
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if (add_list)
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remove_from_list(add_list, res);
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remove_from_list(add_list, res);
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}
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static void pci_bus_distribute_available_resources(struct pci_bus *bus,
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@ -1926,8 +1923,6 @@ static void pci_bridge_distribute_available_resources(struct pci_dev *bridge,
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if (!bridge->is_hotplug_bridge)
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return;
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pci_dbg(bridge, "distributing available resources\n");
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/* Take the initial extra resources from the hotplug port */
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available_io = bridge->resource[PCI_BRIDGE_IO_WINDOW];
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available_mmio = bridge->resource[PCI_BRIDGE_MEM_WINDOW];
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@ -1939,59 +1934,6 @@ static void pci_bridge_distribute_available_resources(struct pci_dev *bridge,
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available_mmio_pref);
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}
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static bool pci_bridge_resources_not_assigned(struct pci_dev *dev)
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{
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const struct resource *r;
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/*
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* Check the child device's resources and if they are not yet
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* assigned it means we are configuring them (not the boot
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* firmware) so we should be able to extend the upstream
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* bridge's (that's the hotplug downstream PCIe port) resources
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* in the same way we do with the normal hotplug case.
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*/
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r = &dev->resource[PCI_BRIDGE_IO_WINDOW];
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if (!r->flags || !(r->flags & IORESOURCE_STARTALIGN))
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return false;
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r = &dev->resource[PCI_BRIDGE_MEM_WINDOW];
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if (!r->flags || !(r->flags & IORESOURCE_STARTALIGN))
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return false;
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r = &dev->resource[PCI_BRIDGE_PREF_MEM_WINDOW];
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if (!r->flags || !(r->flags & IORESOURCE_STARTALIGN))
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return false;
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return true;
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}
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static void pci_root_bus_distribute_available_resources(struct pci_bus *bus,
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struct list_head *add_list)
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{
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struct pci_dev *dev, *bridge = bus->self;
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for_each_pci_bridge(dev, bus) {
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struct pci_bus *b;
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b = dev->subordinate;
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if (!b)
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continue;
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/*
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* Need to check "bridge" here too because it is NULL
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* in case of root bus.
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*/
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if (bridge && pci_bridge_resources_not_assigned(dev)) {
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pci_bridge_distribute_available_resources(bridge, add_list);
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/*
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* There is only PCIe upstream port on the bus
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* so we don't need to go futher.
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*/
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return;
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}
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pci_root_bus_distribute_available_resources(b, add_list);
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}
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}
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/*
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* First try will not touch PCI bridge res.
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* Second and later try will clear small leaf bridge res.
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@ -2031,8 +1973,6 @@ void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus)
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*/
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__pci_bus_size_bridges(bus, add_list);
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pci_root_bus_distribute_available_resources(bus, add_list);
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/* Depth last, allocate resources and update the hardware. */
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__pci_bus_assign_resources(bus, add_list, &fail_head);
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if (add_list)
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