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ARM: mmp: fix timer_read delay 

[ Upstream commit e348b4014c ]

timer_read() was using an empty 100-iteration loop to wait for the
TMR_CVWR register to capture the latest timer counter value. The delay
wasn't long enough. This resulted in CPU idle time being extremely
underreported on PXA168 with CONFIG_NO_HZ_IDLE=y.

Switch to the approach used in the vendor kernel, which implements the
capture delay by reading TMR_CVWR a few times instead.

Fixes: 49cbe78637 ("[ARM] pxa: add base support for Marvell's PXA168 processor line")
Signed-off-by: Doug Brown <doug@schmorgal.com>
Link: https://lore.kernel.org/r/20221204005117.53452-3-doug@schmorgal.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Doug Brown 2022-12-03 16:51:17 -08:00 committed by Greg Kroah-Hartman
parent 65f1ff9011
commit 3c6dfce2c7
1 changed files with 7 additions and 4 deletions
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11
arch/arm/mach-mmp/time.c
View File

@ -43,18 +43,21 @@
static void __iomem *mmp_timer_base = TIMERS_VIRT_BASE; static void __iomem *mmp_timer_base = TIMERS_VIRT_BASE;
/* /*
* FIXME: the timer needs some delay to stablize the counter capture * Read the timer through the CVWR register. Delay is required after requesting
* a read. The CR register cannot be directly read due to metastability issues
* documented in the PXA168 software manual.
*/ */
static inline uint32_t timer_read(void) static inline uint32_t timer_read(void)
{ {
int delay = 100; uint32_t val;
int delay = 3;
__raw_writel(1, mmp_timer_base + TMR_CVWR(1)); __raw_writel(1, mmp_timer_base + TMR_CVWR(1));
while (delay--) while (delay--)
cpu_relax(); val = __raw_readl(mmp_timer_base + TMR_CVWR(1));
return __raw_readl(mmp_timer_base + TMR_CVWR(1)); return val;
} }
static u64 notrace mmp_read_sched_clock(void) static u64 notrace mmp_read_sched_clock(void)