clk: qcom: dispcc-qcm2290: Fix GPLL0_OUT_DIV handling
[ Upstream commit63d56adf04
] GPLL0_OUT_DIV (.fw_name = "gcc_disp_gpll0_div_clk_src") was previously made to reuse the same parent enum entry as GPLL0_OUT_MAIN (.fw_name = "gcc_disp_gpll0_clk_src") in parent_map_2. Resolve it by introducing its own entry in the parent enum and correctly assigning it in disp_cc_parent_map_2[]. Fixes:cc517ea333
("clk: qcom: Add display clock controller driver for QCM2290") Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230412-topic-qcm_dispcc-v2-2-bce7dd512fe4@linaro.org Signed-off-by: Sasha Levin <sashal@kernel.org>
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@ -27,6 +27,7 @@ enum {
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P_DISP_CC_PLL0_OUT_MAIN,
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P_DSI0_PHY_PLL_OUT_BYTECLK,
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P_DSI0_PHY_PLL_OUT_DSICLK,
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P_GPLL0_OUT_DIV,
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P_GPLL0_OUT_MAIN,
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P_SLEEP_CLK,
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};
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@ -83,7 +84,7 @@ static const struct clk_parent_data disp_cc_parent_data_1[] = {
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static const struct parent_map disp_cc_parent_map_2[] = {
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{ P_BI_TCXO_AO, 0 },
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{ P_GPLL0_OUT_MAIN, 4 },
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{ P_GPLL0_OUT_DIV, 4 },
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};
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static const struct clk_parent_data disp_cc_parent_data_2[] = {
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@ -152,8 +153,8 @@ static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = {
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static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = {
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F(19200000, P_BI_TCXO_AO, 1, 0, 0),
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F(37500000, P_GPLL0_OUT_MAIN, 8, 0, 0),
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F(75000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
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F(37500000, P_GPLL0_OUT_DIV, 8, 0, 0),
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F(75000000, P_GPLL0_OUT_DIV, 4, 0, 0),
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{ }
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};
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