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dt-bindings: ufs: ti: Fix address properties handling 

The ti,j721e-ufs schema and example have a couple of problems related to
address properties. First, the default #size-cells and #address-cells
are 1 for examples, so they need to be overriden with a bus node.
Second, address translation for the child ufs node is broken because
'ranges', '#address-cells', and '#size-cells' are missing from the
schema.

Acked-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Rob Herring <robh@kernel.org>
This commit is contained in:
Rob Herring 2020-05-12 15:45:41 -05:00
parent 3c9ab53f03
commit 346dda3167
1 changed files with 35 additions and 20 deletions
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55
Documentation/devicetree/bindings/ufs/ti,j721e-ufs.yaml
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@ -25,6 +25,14 @@ properties:
power-domains:
maxItems: 1
"#address-cells":
const: 2
"#size-cells":
const: 2
ranges: true
required:
- compatible
- reg
@ -44,25 +52,32 @@ examples:
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
ufs_wrapper: ufs-wrapper@4e80000 {
compatible = "ti,j721e-ufs";
reg = <0x0 0x4e80000 0x0 0x100>;
power-domains = <&k3_pds 277>;
clocks = <&k3_clks 277 1>;
assigned-clocks = <&k3_clks 277 1>;
assigned-clock-parents = <&k3_clks 277 4>;
#address-cells = <2>;
#size-cells = <2>;
bus {
#address-cells = <2>;
#size-cells = <2>;
ufs@4e84000 {
compatible = "cdns,ufshc-m31-16nm", "jedec,ufs-2.0";
reg = <0x0 0x4e84000 0x0 0x10000>;
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
freq-table-hz = <19200000 19200000>;
power-domains = <&k3_pds 277>;
clocks = <&k3_clks 277 1>;
assigned-clocks = <&k3_clks 277 1>;
assigned-clock-parents = <&k3_clks 277 4>;
clock-names = "core_clk";
};
ufs-wrapper@4e80000 {
compatible = "ti,j721e-ufs";
reg = <0x0 0x4e80000 0x0 0x100>;
power-domains = <&k3_pds 277>;
clocks = <&k3_clks 277 1>;
assigned-clocks = <&k3_clks 277 1>;
assigned-clock-parents = <&k3_clks 277 4>;
ranges = <0x0 0x0 0x0 0x4e80000 0x0 0x14000>;
#address-cells = <2>;
#size-cells = <2>;
ufs@4000 {
compatible = "cdns,ufshc-m31-16nm", "jedec,ufs-2.0";
reg = <0x0 0x4000 0x0 0x10000>;
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
freq-table-hz = <19200000 19200000>;
power-domains = <&k3_pds 277>;
clocks = <&k3_clks 277 1>;
assigned-clocks = <&k3_clks 277 1>;
assigned-clock-parents = <&k3_clks 277 4>;
clock-names = "core_clk";
};
};
};