arm64: Rename ARM64_WORKAROUND_2966298
commit 546b7cde9b1dd36089649101b75266564600ffe5 upstream. In preparation to apply ARM64_WORKAROUND_2966298 for multiple errata, rename the kconfig and capability. No functional change. Cc: stable@vger.kernel.org Signed-off-by: Rob Herring <robh@kernel.org> Reviewed-by: Mark Rutland <mark.rutland@arm.com> Link: https://lore.kernel.org/r/20240110-arm-errata-a510-v1-1-d02bc51aeeee@kernel.org Signed-off-by: Will Deacon <will@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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@ -983,8 +983,12 @@ config ARM64_ERRATUM_2457168
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If unsure, say Y.
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config ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD
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bool
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config ARM64_ERRATUM_2966298
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bool "Cortex-A520: 2966298: workaround for speculatively executed unprivileged load"
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select ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD
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default y
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help
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This option adds the workaround for ARM Cortex-A520 erratum 2966298.
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@ -723,10 +723,10 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
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.cpu_enable = cpu_clear_bf16_from_user_emulation,
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},
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#endif
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#ifdef CONFIG_ARM64_ERRATUM_2966298
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#ifdef CONFIG_ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD
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{
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.desc = "ARM erratum 2966298",
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.capability = ARM64_WORKAROUND_2966298,
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.capability = ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD,
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/* Cortex-A520 r0p0 - r0p1 */
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ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A520, 0, 0, 1),
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},
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@ -419,7 +419,7 @@ alternative_else_nop_endif
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ldp x28, x29, [sp, #16 * 14]
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.if \el == 0
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alternative_if ARM64_WORKAROUND_2966298
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alternative_if ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD
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tlbi vale1, xzr
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dsb nsh
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alternative_else_nop_endif
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@ -71,7 +71,6 @@ WORKAROUND_2064142
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WORKAROUND_2077057
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WORKAROUND_2457168
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WORKAROUND_2658417
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WORKAROUND_2966298
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WORKAROUND_AMPERE_AC03_CPU_38
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WORKAROUND_TRBE_OVERWRITE_FILL_MODE
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WORKAROUND_TSB_FLUSH_FAILURE
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@ -87,3 +86,4 @@ WORKAROUND_NVIDIA_CARMEL_CNP
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WORKAROUND_QCOM_FALKOR_E1003
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WORKAROUND_REPEAT_TLBI
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WORKAROUND_SPECULATIVE_AT
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WORKAROUND_SPECULATIVE_UNPRIV_LOAD
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