OrgACRN
/
acrn-kernel
mirror of https://github.com/projectacrn/acrn-kernel.git
1
0
Fork 0
Code Issues Releases Wiki Activity

arm64: Rename ARM64_WORKAROUND_2966298 

commit 546b7cde9b1dd36089649101b75266564600ffe5 upstream.

In preparation to apply ARM64_WORKAROUND_2966298 for multiple errata,
rename the kconfig and capability. No functional change.

Cc: stable@vger.kernel.org
Signed-off-by: Rob Herring <robh@kernel.org>
Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Link: https://lore.kernel.org/r/20240110-arm-errata-a510-v1-1-d02bc51aeeee@kernel.org
Signed-off-by: Will Deacon <will@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Rob Herring 2024-01-10 11:29:20 -06:00 committed by Greg Kroah-Hartman
parent 9fec4db7ff
commit 2b1dc0666e
4 changed files with 8 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
arch/arm64/Kconfig
View File

@ -983,8 +983,12 @@ config ARM64_ERRATUM_2457168
If unsure, say Y. If unsure, say Y.
config ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD
bool
config ARM64_ERRATUM_2966298 config ARM64_ERRATUM_2966298
bool "Cortex-A520: 2966298: workaround for speculatively executed unprivileged load" bool "Cortex-A520: 2966298: workaround for speculatively executed unprivileged load"
select ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD
default y default y
help help
This option adds the workaround for ARM Cortex-A520 erratum 2966298. This option adds the workaround for ARM Cortex-A520 erratum 2966298.

4
arch/arm64/kernel/cpu_errata.c
View File

@ -723,10 +723,10 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
.cpu_enable = cpu_clear_bf16_from_user_emulation, .cpu_enable = cpu_clear_bf16_from_user_emulation,
}, },
#endif #endif
#ifdef CONFIG_ARM64_ERRATUM_2966298 #ifdef CONFIG_ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD
{ {
.desc = "ARM erratum 2966298", .desc = "ARM erratum 2966298",
.capability = ARM64_WORKAROUND_2966298, .capability = ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD,
/* Cortex-A520 r0p0 - r0p1 */ /* Cortex-A520 r0p0 - r0p1 */
ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A520, 0, 0, 1), ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A520, 0, 0, 1),
}, },

2
arch/arm64/kernel/entry.S
View File

@ -419,7 +419,7 @@ alternative_else_nop_endif
ldp x28, x29, [sp, #16 * 14] ldp x28, x29, [sp, #16 * 14]
.if \el == 0 .if \el == 0
alternative_if ARM64_WORKAROUND_2966298 alternative_if ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD
tlbi vale1, xzr tlbi vale1, xzr
dsb nsh dsb nsh
alternative_else_nop_endif alternative_else_nop_endif

2
arch/arm64/tools/cpucaps
View File

@ -71,7 +71,6 @@ WORKAROUND_2064142
WORKAROUND_2077057 WORKAROUND_2077057
WORKAROUND_2457168 WORKAROUND_2457168
WORKAROUND_2658417 WORKAROUND_2658417
WORKAROUND_2966298
WORKAROUND_AMPERE_AC03_CPU_38 WORKAROUND_AMPERE_AC03_CPU_38
WORKAROUND_TRBE_OVERWRITE_FILL_MODE WORKAROUND_TRBE_OVERWRITE_FILL_MODE
WORKAROUND_TSB_FLUSH_FAILURE WORKAROUND_TSB_FLUSH_FAILURE
@ -87,3 +86,4 @@ WORKAROUND_NVIDIA_CARMEL_CNP
WORKAROUND_QCOM_FALKOR_E1003 WORKAROUND_QCOM_FALKOR_E1003
WORKAROUND_REPEAT_TLBI WORKAROUND_REPEAT_TLBI
WORKAROUND_SPECULATIVE_AT WORKAROUND_SPECULATIVE_AT
WORKAROUND_SPECULATIVE_UNPRIV_LOAD