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pinctrl: amd: Unify debounce handling into amd_pinconf_set() 

Debounce handling is done in two different entry points in the driver.
Unify this to make sure that it's always handled the same.

Tested-by: Jan Visser <starquake@linuxeverywhere.org>
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
Link: https://lore.kernel.org/r/20230705133005.577-5-mario.limonciello@amd.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Mario Limonciello 2023-07-05 08:30:05 -05:00 committed by Linus Walleij
parent 3f62312d04
commit 283c5ce7da
1 changed files with 5 additions and 16 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

21
drivers/pinctrl/pinctrl-amd.c
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@ -116,16 +116,12 @@ static void amd_gpio_set_value(struct gpio_chip *gc, unsigned offset, int value)
raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
} }
static int amd_gpio_set_debounce(struct gpio_chip *gc, unsigned offset, static int amd_gpio_set_debounce(struct amd_gpio *gpio_dev, unsigned int offset,
unsigned debounce) unsigned int debounce)
{ {
u32 time; u32 time;
u32 pin_reg; u32 pin_reg;
int ret = 0; int ret = 0;
unsigned long flags;
struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
raw_spin_lock_irqsave(&gpio_dev->lock, flags);
/* Use special handling for Pin0 debounce */ /* Use special handling for Pin0 debounce */
if (offset == 0) { if (offset == 0) {
@ -184,7 +180,6 @@ static int amd_gpio_set_debounce(struct gpio_chip *gc, unsigned offset,
pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF); pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF);
} }
writel(pin_reg, gpio_dev->base + offset * 4); writel(pin_reg, gpio_dev->base + offset * 4);
raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
return ret; return ret;
} }
@ -782,9 +777,8 @@ static int amd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
switch (param) { switch (param) {
case PIN_CONFIG_INPUT_DEBOUNCE: case PIN_CONFIG_INPUT_DEBOUNCE:
pin_reg &= ~DB_TMR_OUT_MASK; ret = amd_gpio_set_debounce(gpio_dev, pin, arg);
pin_reg |= arg & DB_TMR_OUT_MASK; goto out_unlock;
break;
case PIN_CONFIG_BIAS_PULL_DOWN: case PIN_CONFIG_BIAS_PULL_DOWN:
pin_reg &= ~BIT(PULL_DOWN_ENABLE_OFF); pin_reg &= ~BIT(PULL_DOWN_ENABLE_OFF);
@ -811,6 +805,7 @@ static int amd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
writel(pin_reg, gpio_dev->base + pin*4); writel(pin_reg, gpio_dev->base + pin*4);
} }
out_unlock:
raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
return ret; return ret;
@ -857,12 +852,6 @@ static int amd_gpio_set_config(struct gpio_chip *gc, unsigned int pin,
{ {
struct amd_gpio *gpio_dev = gpiochip_get_data(gc); struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
if (pinconf_to_config_param(config) == PIN_CONFIG_INPUT_DEBOUNCE) {
u32 debounce = pinconf_to_config_argument(config);
return amd_gpio_set_debounce(gc, pin, debounce);
}
return amd_pinconf_set(gpio_dev->pctrl, pin, &config, 1); return amd_pinconf_set(gpio_dev->pctrl, pin, &config, 1);
} }