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mips: bmips: dts: add BCM6362 reset controller support 

BCM6362 SoCs have a reset controller for certain components.

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
This commit is contained in:
Álvaro Fernández Rojas 2020-06-17 12:50:38 +02:00 committed by Thomas Bogendoerfer
parent 8079cfba4c
commit 226383600b
2 changed files with 28 additions and 0 deletions
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6
arch/mips/boot/dts/brcm/bcm6362.dtsi
View File

@ -70,6 +70,12 @@ reboot: syscon-reboot@10000008 {
mask = <0x1>; mask = <0x1>;
}; };
periph_rst: reset-controller@10000010 {
compatible = "brcm,bcm6345-reset";
reg = <0x10000010 0x4>;
#reset-cells = <1>;
};
periph_intc: interrupt-controller@10000020 { periph_intc: interrupt-controller@10000020 {
compatible = "brcm,bcm6345-l1-intc"; compatible = "brcm,bcm6345-l1-intc";
reg = <0x10000020 0x10>, reg = <0x10000020 0x10>,

22
include/dt-bindings/reset/bcm6362-reset.h Normal file
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@ -0,0 +1,22 @@
/* SPDX-License-Identifier: GPL-2.0+ */
#ifndef __DT_BINDINGS_RESET_BCM6362_H
#define __DT_BINDINGS_RESET_BCM6362_H
#define BCM6362_RST_SPI 0
#define BCM6362_RST_IPSEC 1
#define BCM6362_RST_EPHY 2
#define BCM6362_RST_SAR 3
#define BCM6362_RST_ENETSW 4
#define BCM6362_RST_USBD 5
#define BCM6362_RST_USBH 6
#define BCM6362_RST_PCM 7
#define BCM6362_RST_PCIE_CORE 8
#define BCM6362_RST_PCIE 9
#define BCM6362_RST_PCIE_EXT 10
#define BCM6362_RST_WLAN_SHIM 11
#define BCM6362_RST_DDR_PHY 12
#define BCM6362_RST_FAP 13
#define BCM6362_RST_WLAN_UBUS 14
#endif /* __DT_BINDINGS_RESET_BCM6362_H */