LoongArch: Remove obsolete mentions of vcsr
The `vcsr` only exists in the old hardware design, it isn't used in any shipped hardware from Loongson-3A5000 on. Both scalar FP and LSX/LASX instructions use the `fcsr` as their control and status registers now. For example, the RM control bit in fcsr0 is shared by FP, LSX and LASX instructions. Particularly, fcsr16 to fcsr31 are reserved for LSX/LASX now, access to these registers has no visible effect if LSX/LASX is enabled, and will cause SXD/ASXD exceptions if LSX/LASX is not enabled. So, mentions of vcsr are obsolete in the first place (it was just used for debugging), let's remove them. Reviewed-by: WANG Xuerui <git@xen0n.name> Signed-off-by: Qi Hu <huqi@loongson.cn> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
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@ -48,6 +48,5 @@
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#define fcsr1 $r1
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#define fcsr2 $r2
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#define fcsr3 $r3
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#define vcsr16 $r16
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#endif /* _ASM_FPREGDEF_H */
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@ -80,7 +80,6 @@ BUILD_FPR_ACCESS(64)
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struct loongarch_fpu {
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unsigned int fcsr;
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unsigned int vcsr;
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uint64_t fcc; /* 8x8 */
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union fpureg fpr[NUM_FPU_REGS];
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};
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@ -161,7 +160,6 @@ struct thread_struct {
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*/ \
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.fpu = { \
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.fcsr = 0, \
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.vcsr = 0, \
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.fcc = 0, \
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.fpr = {{{0,},},}, \
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}, \
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@ -166,7 +166,6 @@ void output_thread_fpu_defines(void)
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OFFSET(THREAD_FCSR, loongarch_fpu, fcsr);
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OFFSET(THREAD_FCC, loongarch_fpu, fcc);
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OFFSET(THREAD_VCSR, loongarch_fpu, vcsr);
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BLANK();
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}
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@ -146,16 +146,6 @@
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movgr2fcsr fcsr0, \tmp0
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.endm
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.macro sc_save_vcsr base, tmp0
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movfcsr2gr \tmp0, vcsr16
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EX st.w \tmp0, \base, 0
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.endm
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.macro sc_restore_vcsr base, tmp0
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EX ld.w \tmp0, \base, 0
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movgr2fcsr vcsr16, \tmp0
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.endm
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/*
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* Save a thread's fp context.
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*/
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