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riscv: dts: microchip: use an mpfs specific l2 compatible 

PolarFire SoC does not have the same l2 cache controller as the fu540,
featuring an extra interrupt. Appease the devicetree checker overlords
by adding a PolarFire SoC specific compatible to fix the below sort of
warnings:

mpfs-polarberry.dtb: cache-controller@2010000: interrupts: [[1], [3], [4], [2]] is too long

Fixes: 0fa6107eca ("RISC-V: Initial DTS for Microchip ICICLE board")
Fixes: 34fc9cc3ae ("riscv: dts: microchip: correct L2 cache interrupts")
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
This commit is contained in:
Conor Dooley 2022-08-25 19:04:18 +01:00
parent 17e4732d1d
commit 0dec364ffe
1 changed files with 1 additions and 1 deletions
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2
arch/riscv/boot/dts/microchip/mpfs.dtsi
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@ -185,7 +185,7 @@ soc {
ranges;
cctrllr: cache-controller@2010000 {
compatible = "sifive,fu540-c000-ccache", "cache";
compatible = "microchip,mpfs-ccache", "sifive,fu540-c000-ccache", "cache";
reg = <0x0 0x2010000 0x0 0x1000>;
cache-block-size = <64>;
cache-level = <2>;