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clk: mxl: Switch from direct readl/writel based IO to regmap based IO 

Earlier version of driver used direct io remapped register read
writes using readl/writel. But we need secure boot access which
is only possible when registers are read & written using regmap.
This is because the security bus/hook is written & coupled only
with regmap layer.

Switch the driver from direct readl/writel based register accesses
to regmap based register accesses.

Additionally, update the license headers to latest status.

Reviewed-by: Yi xin Zhu <yzhu@maxlinear.com>
Signed-off-by: Rahul Tanwar <rtanwar@maxlinear.com>
Link: https://lore.kernel.org/r/2610331918206e0e3bd18babb39393a558fb34f9.1665642720.git.rtanwar@maxlinear.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
Rahul Tanwar 2022-10-13 14:48:30 +08:00 committed by Stephen Boyd
parent 9abf2313ad
commit 036177310b
5 changed files with 42 additions and 29 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
drivers/clk/x86/Kconfig
View File

@ -1,8 +1,9 @@
# SPDX-License-Identifier: GPL-2.0-only
config CLK_LGM_CGU
depends on OF && HAS_IOMEM && (X86 || COMPILE_TEST)
select MFD_SYSCON
select OF_EARLY_FLATTREE
bool "Clock driver for Lightning Mountain(LGM) platform"
help
Clock Generation Unit(CGU) driver for Intel Lightning Mountain(LGM)
network processor SoC.
Clock Generation Unit(CGU) driver for MaxLinear's x86 based
Lightning Mountain(LGM) network processor SoC.

10
drivers/clk/x86/clk-cgu-pll.c
View File

@ -1,8 +1,9 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2020-2022 MaxLinear, Inc.
* Copyright (C) 2020 Intel Corporation.
* Zhu YiXin <yixin.zhu@intel.com>
* Rahul Tanwar <rahul.tanwar@intel.com>
* Zhu Yixin <yzhu@maxlinear.com>
* Rahul Tanwar <rtanwar@maxlinear.com>
*/
#include <linux/clk-provider.h>
@ -76,8 +77,9 @@ static int lgm_pll_enable(struct clk_hw *hw)
spin_lock_irqsave(&pll->lock, flags);
lgm_set_clk_val(pll->membase, pll->reg, 0, 1, 1);
ret = readl_poll_timeout_atomic(pll->membase + pll->reg,
val, (val & 0x1), 1, 100);
ret = regmap_read_poll_timeout_atomic(pll->membase, pll->reg,
val, (val & 0x1), 1, 100);
spin_unlock_irqrestore(&pll->lock, flags);
return ret;

5
drivers/clk/x86/clk-cgu.c
View File

@ -1,8 +1,9 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2020-2022 MaxLinear, Inc.
* Copyright (C) 2020 Intel Corporation.
* Zhu YiXin <yixin.zhu@intel.com>
* Rahul Tanwar <rahul.tanwar@intel.com>
* Zhu Yixin <yzhu@maxlinear.com>
* Rahul Tanwar <rtanwar@maxlinear.com>
*/
#include <linux/clk-provider.h>
#include <linux/device.h>

38
drivers/clk/x86/clk-cgu.h
View File

@ -1,18 +1,19 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright(c) 2020 Intel Corporation.
* Zhu YiXin <yixin.zhu@intel.com>
* Rahul Tanwar <rahul.tanwar@intel.com>
* Copyright (C) 2020-2022 MaxLinear, Inc.
* Copyright (C) 2020 Intel Corporation.
* Zhu Yixin <yzhu@maxlinear.com>
* Rahul Tanwar <rtanwar@maxlinear.com>
*/
#ifndef __CLK_CGU_H
#define __CLK_CGU_H
#include <linux/io.h>
#include <linux/regmap.h>
struct lgm_clk_mux {
struct clk_hw hw;
void __iomem *membase;
struct regmap *membase;
unsigned int reg;
u8 shift;
u8 width;
@ -22,7 +23,7 @@ struct lgm_clk_mux {
struct lgm_clk_divider {
struct clk_hw hw;
void __iomem *membase;
struct regmap *membase;
unsigned int reg;
u8 shift;
u8 width;
@ -35,7 +36,7 @@ struct lgm_clk_divider {
struct lgm_clk_ddiv {
struct clk_hw hw;
void __iomem *membase;
struct regmap *membase;
unsigned int reg;
u8 shift0;
u8 width0;
@ -53,7 +54,7 @@ struct lgm_clk_ddiv {
struct lgm_clk_gate {
struct clk_hw hw;
void __iomem *membase;
struct regmap *membase;
unsigned int reg;
u8 shift;
unsigned long flags;
@ -77,7 +78,7 @@ enum lgm_clk_type {
* @clk_data: array of hw clocks and clk number.
*/
struct lgm_clk_provider {
void __iomem *membase;
struct regmap *membase;
struct device_node *np;
struct device *dev;
struct clk_hw_onecell_data clk_data;
@ -92,7 +93,7 @@ enum pll_type {
struct lgm_clk_pll {
struct clk_hw hw;
void __iomem *membase;
struct regmap *membase;
unsigned int reg;
unsigned long flags;
enum pll_type type;
@ -300,29 +301,32 @@ struct lgm_clk_branch {
.div = _d, \
}
static inline void lgm_set_clk_val(void __iomem *membase, u32 reg,
static inline void lgm_set_clk_val(struct regmap *membase, u32 reg,
u8 shift, u8 width, u32 set_val)
{
u32 mask = (GENMASK(width - 1, 0) << shift);
u32 regval;
regval = readl(membase + reg);
regval = (regval & ~mask) | ((set_val << shift) & mask);
writel(regval, membase + reg);
regmap_update_bits(membase, reg, mask, set_val << shift);
}
static inline u32 lgm_get_clk_val(void __iomem *membase, u32 reg,
static inline u32 lgm_get_clk_val(struct regmap *membase, u32 reg,
u8 shift, u8 width)
{
u32 mask = (GENMASK(width - 1, 0) << shift);
u32 val;
val = readl(membase + reg);
if (regmap_read(membase, reg, &val)) {
WARN_ONCE(1, "Failed to read clk reg: 0x%x\n", reg);
return 0;
}
val = (val & mask) >> shift;
return val;
}
int lgm_clk_register_branches(struct lgm_clk_provider *ctx,
const struct lgm_clk_branch *list,
unsigned int nr_clk);

13
drivers/clk/x86/clk-lgm.c
View File

@ -1,10 +1,12 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2020-2022 MaxLinear, Inc.
* Copyright (C) 2020 Intel Corporation.
* Zhu YiXin <yixin.zhu@intel.com>
* Rahul Tanwar <rahul.tanwar@intel.com>
* Zhu Yixin <yzhu@maxlinear.com>
* Rahul Tanwar <rtanwar@maxlinear.com>
*/
#include <linux/clk-provider.h>
#include <linux/mfd/syscon.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <dt-bindings/clock/intel,lgm-clk.h>
@ -433,9 +435,12 @@ static int lgm_cgu_probe(struct platform_device *pdev)
ctx->clk_data.num = CLK_NR_CLKS;
ctx->membase = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(ctx->membase))
ctx->membase = syscon_node_to_regmap(np);
if (IS_ERR_OR_NULL(ctx->membase)) {
dev_err(dev, "Failed to get clk CGU iomem\n");
return PTR_ERR(ctx->membase);
}
ctx->np = np;
ctx->dev = dev;