KVM: x86/speculation: Disable Fill buffer clear within guests
The enumeration of MD_CLEAR in CPUID(EAX=7,ECX=0).EDX{bit 10} is not an accurate indicator on all CPUs of whether the VERW instruction will overwrite fill buffers. FB_CLEAR enumeration in IA32_ARCH_CAPABILITIES{bit 17} covers the case of CPUs that are not vulnerable to MDS/TAA, indicating that microcode does overwrite fill buffers. Guests running in VMM environments may not be aware of all the capabilities/vulnerabilities of the host CPU. Specifically, a guest may apply MDS/TAA mitigations when a virtual CPU is enumerated as vulnerable to MDS/TAA even when the physical CPU is not. On CPUs that enumerate FB_CLEAR_CTRL the VMM may set FB_CLEAR_DIS to skip overwriting of fill buffers by the VERW instruction. This is done by setting FB_CLEAR_DIS during VMENTER and resetting on VMEXIT. For guests that enumerate FB_CLEAR (explicitly asking for fill buffer clear capability) the VMM will not use FB_CLEAR_DIS. Irrespective of guest state, host overwrites CPU buffers before VMENTER to protect itself from an MMIO capable guest, as part of mitigation for MMIO Stale Data vulnerabilities. Signed-off-by: Pawan Gupta <pawan.kumar.gupta@linux.intel.com> Signed-off-by: Borislav Petkov <bp@suse.de>
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@ -133,6 +133,11 @@
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* VERW clears CPU fill buffer
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* even on MDS_NO CPUs.
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*/
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#define ARCH_CAP_FB_CLEAR_CTRL BIT(18) /*
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* MSR_IA32_MCU_OPT_CTRL[FB_CLEAR_DIS]
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* bit available to control VERW
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* behavior.
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*/
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#define MSR_IA32_FLUSH_CMD 0x0000010b
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#define L1D_FLUSH BIT(0) /*
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@ -150,6 +155,7 @@
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#define MSR_IA32_MCU_OPT_CTRL 0x00000123
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#define RNGDS_MITG_DIS BIT(0) /* SRBDS support */
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#define RTM_ALLOW BIT(1) /* TSX development mode */
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#define FB_CLEAR_DIS BIT(3) /* CPU Fill buffer clear disable */
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#define MSR_IA32_SYSENTER_CS 0x00000174
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#define MSR_IA32_SYSENTER_ESP 0x00000175
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@ -229,6 +229,9 @@ static const struct {
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#define L1D_CACHE_ORDER 4
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static void *vmx_l1d_flush_pages;
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/* Control for disabling CPU Fill buffer clear */
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static bool __read_mostly vmx_fb_clear_ctrl_available;
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static int vmx_setup_l1d_flush(enum vmx_l1d_flush_state l1tf)
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{
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struct page *page;
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@ -360,6 +363,60 @@ static int vmentry_l1d_flush_get(char *s, const struct kernel_param *kp)
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return sprintf(s, "%s\n", vmentry_l1d_param[l1tf_vmx_mitigation].option);
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}
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static void vmx_setup_fb_clear_ctrl(void)
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{
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u64 msr;
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if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES) &&
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!boot_cpu_has_bug(X86_BUG_MDS) &&
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!boot_cpu_has_bug(X86_BUG_TAA)) {
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rdmsrl(MSR_IA32_ARCH_CAPABILITIES, msr);
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if (msr & ARCH_CAP_FB_CLEAR_CTRL)
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vmx_fb_clear_ctrl_available = true;
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}
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}
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static __always_inline void vmx_disable_fb_clear(struct vcpu_vmx *vmx)
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{
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u64 msr;
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if (!vmx->disable_fb_clear)
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return;
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rdmsrl(MSR_IA32_MCU_OPT_CTRL, msr);
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msr |= FB_CLEAR_DIS;
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wrmsrl(MSR_IA32_MCU_OPT_CTRL, msr);
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/* Cache the MSR value to avoid reading it later */
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vmx->msr_ia32_mcu_opt_ctrl = msr;
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}
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static __always_inline void vmx_enable_fb_clear(struct vcpu_vmx *vmx)
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{
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if (!vmx->disable_fb_clear)
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return;
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vmx->msr_ia32_mcu_opt_ctrl &= ~FB_CLEAR_DIS;
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wrmsrl(MSR_IA32_MCU_OPT_CTRL, vmx->msr_ia32_mcu_opt_ctrl);
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}
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static void vmx_update_fb_clear_dis(struct kvm_vcpu *vcpu, struct vcpu_vmx *vmx)
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{
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vmx->disable_fb_clear = vmx_fb_clear_ctrl_available;
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/*
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* If guest will not execute VERW, there is no need to set FB_CLEAR_DIS
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* at VMEntry. Skip the MSR read/write when a guest has no use case to
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* execute VERW.
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*/
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if ((vcpu->arch.arch_capabilities & ARCH_CAP_FB_CLEAR) ||
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((vcpu->arch.arch_capabilities & ARCH_CAP_MDS_NO) &&
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(vcpu->arch.arch_capabilities & ARCH_CAP_TAA_NO) &&
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(vcpu->arch.arch_capabilities & ARCH_CAP_PSDP_NO) &&
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(vcpu->arch.arch_capabilities & ARCH_CAP_FBSDP_NO) &&
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(vcpu->arch.arch_capabilities & ARCH_CAP_SBDR_SSDP_NO)))
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vmx->disable_fb_clear = false;
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}
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static const struct kernel_param_ops vmentry_l1d_flush_ops = {
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.set = vmentry_l1d_flush_set,
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.get = vmentry_l1d_flush_get,
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@ -2252,6 +2309,10 @@ static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
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ret = kvm_set_msr_common(vcpu, msr_info);
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}
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/* FB_CLEAR may have changed, also update the FB_CLEAR_DIS behavior */
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if (msr_index == MSR_IA32_ARCH_CAPABILITIES)
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vmx_update_fb_clear_dis(vcpu, vmx);
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return ret;
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}
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@ -4553,6 +4614,8 @@ static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
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kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
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vpid_sync_context(vmx->vpid);
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vmx_update_fb_clear_dis(vcpu, vmx);
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}
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static void vmx_enable_irq_window(struct kvm_vcpu *vcpu)
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@ -6777,6 +6840,8 @@ static noinstr void vmx_vcpu_enter_exit(struct kvm_vcpu *vcpu,
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kvm_arch_has_assigned_device(vcpu->kvm))
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mds_clear_cpu_buffers();
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vmx_disable_fb_clear(vmx);
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if (vcpu->arch.cr2 != native_read_cr2())
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native_write_cr2(vcpu->arch.cr2);
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@ -6785,6 +6850,8 @@ static noinstr void vmx_vcpu_enter_exit(struct kvm_vcpu *vcpu,
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vcpu->arch.cr2 = native_read_cr2();
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vmx_enable_fb_clear(vmx);
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guest_state_exit_irqoff();
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}
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@ -8185,6 +8252,8 @@ static int __init vmx_init(void)
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return r;
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}
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vmx_setup_fb_clear_ctrl();
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for_each_possible_cpu(cpu) {
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INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
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@ -348,6 +348,8 @@ struct vcpu_vmx {
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u64 msr_ia32_feature_control_valid_bits;
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/* SGX Launch Control public key hash */
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u64 msr_ia32_sgxlepubkeyhash[4];
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u64 msr_ia32_mcu_opt_ctrl;
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bool disable_fb_clear;
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struct pt_desc pt_desc;
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struct lbr_desc lbr_desc;
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@ -1587,6 +1587,9 @@ static u64 kvm_get_arch_capabilities(void)
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*/
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}
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/* Guests don't need to know "Fill buffer clear control" exists */
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data &= ~ARCH_CAP_FB_CLEAR_CTRL;
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return data;
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}
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@ -133,6 +133,11 @@
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* VERW clears CPU fill buffer
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* even on MDS_NO CPUs.
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*/
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#define ARCH_CAP_FB_CLEAR_CTRL BIT(18) /*
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* MSR_IA32_MCU_OPT_CTRL[FB_CLEAR_DIS]
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* bit available to control VERW
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* behavior.
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*/
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#define MSR_IA32_FLUSH_CMD 0x0000010b
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#define L1D_FLUSH BIT(0) /*
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@ -150,6 +155,7 @@
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#define MSR_IA32_MCU_OPT_CTRL 0x00000123
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#define RNGDS_MITG_DIS BIT(0) /* SRBDS support */
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#define RTM_ALLOW BIT(1) /* TSX development mode */
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#define FB_CLEAR_DIS BIT(3) /* CPU Fill buffer clear disable */
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#define MSR_IA32_SYSENTER_CS 0x00000174
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#define MSR_IA32_SYSENTER_ESP 0x00000175
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