2005-04-17 06:20:36 +08:00
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1999 by Kaz Kojima
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*
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* Defitions for the address spaces of the SH-4 CPUs.
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*/
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#ifndef __ASM_CPU_SH4_ADDRSPACE_H
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#define __ASM_CPU_SH4_ADDRSPACE_H
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/* Detailed P4SEG */
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#define P4SEG_STORE_QUE (P4SEG)
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#define P4SEG_IC_ADDR 0xf0000000
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#define P4SEG_IC_DATA 0xf1000000
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#define P4SEG_ITLB_ADDR 0xf2000000
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#define P4SEG_ITLB_DATA 0xf3000000
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#define P4SEG_OC_ADDR 0xf4000000
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#define P4SEG_OC_DATA 0xf5000000
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#define P4SEG_TLB_ADDR 0xf6000000
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#define P4SEG_TLB_DATA 0xf7000000
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#define P4SEG_REG_BASE 0xff000000
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2006-09-27 14:59:17 +08:00
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#define PA_AREA5_IO 0xb4000000 /* Area 5 IO Memory */
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#define PA_AREA6_IO 0xb8000000 /* Area 6 IO Memory */
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2005-04-17 06:20:36 +08:00
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#endif /* __ASM_CPU_SH4_ADDRSPACE_H */
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