139 lines
3.3 KiB
C
139 lines
3.3 KiB
C
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// SPDX-License-Identifier: GPL-2.0
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/*
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* SGI IP30 miscellaneous setup bits.
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*
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* Copyright (C) 2004-2007 Stanislaw Skowronek <skylark@unaligned.org>
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* 2007 Joshua Kinard <kumba@gentoo.org>
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* 2009 Johannes Dickgreber <tanzy@gmx.de>
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*/
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/percpu.h>
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#include <linux/memblock.h>
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#include <asm/smp-ops.h>
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#include <asm/sgialib.h>
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#include <asm/time.h>
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#include <asm/sgi/heart.h>
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#include "ip30-common.h"
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/* Structure of accessible HEART registers located in XKPHYS space. */
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struct ip30_heart_regs __iomem *heart_regs = HEART_XKPHYS_BASE;
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/*
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* ARCS will report up to the first 1GB of
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* memory if queried. Anything beyond that
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* is marked as reserved.
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*/
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#define IP30_MAX_PROM_MEMORY _AC(0x40000000, UL)
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/*
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* Memory in the Octane starts at 512MB
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*/
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#define IP30_MEMORY_BASE _AC(0x20000000, UL)
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/*
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* If using ARCS to probe for memory, then
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* remaining memory will start at this offset.
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*/
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#define IP30_REAL_MEMORY_START (IP30_MEMORY_BASE + IP30_MAX_PROM_MEMORY)
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#define MEM_SHIFT(x) ((x) >> 20)
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static void __init ip30_mem_init(void)
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{
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unsigned long total_mem;
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phys_addr_t addr;
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phys_addr_t size;
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u32 memcfg;
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int i;
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total_mem = 0;
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for (i = 0; i < HEART_MEMORY_BANKS; i++) {
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memcfg = __raw_readl(&heart_regs->mem_cfg.l[i]);
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if (!(memcfg & HEART_MEMCFG_VALID))
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continue;
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addr = memcfg & HEART_MEMCFG_ADDR_MASK;
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addr <<= HEART_MEMCFG_UNIT_SHIFT;
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addr += IP30_MEMORY_BASE;
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size = memcfg & HEART_MEMCFG_SIZE_MASK;
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size >>= HEART_MEMCFG_SIZE_SHIFT;
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size += 1;
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size <<= HEART_MEMCFG_UNIT_SHIFT;
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total_mem += size;
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if (addr >= IP30_REAL_MEMORY_START)
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memblock_free(addr, size);
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else if ((addr + size) > IP30_REAL_MEMORY_START)
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memblock_free(IP30_REAL_MEMORY_START,
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size - IP30_MAX_PROM_MEMORY);
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}
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pr_info("Detected %luMB of physical memory.\n", MEM_SHIFT(total_mem));
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}
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/**
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* ip30_cpu_time_init - platform time initialization.
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*/
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static void __init ip30_cpu_time_init(void)
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{
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int cpu = smp_processor_id();
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u64 heart_compare;
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unsigned int start, end;
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int time_diff;
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heart_compare = (heart_read(&heart_regs->count) +
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(HEART_CYCLES_PER_SEC / 10));
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start = read_c0_count();
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while ((heart_read(&heart_regs->count) - heart_compare) & 0x800000)
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cpu_relax();
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end = read_c0_count();
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time_diff = (int)end - (int)start;
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mips_hpt_frequency = time_diff * 10;
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pr_info("IP30: CPU%d: %d MHz CPU detected.\n", cpu,
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(mips_hpt_frequency * 2) / 1000000);
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}
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void __init ip30_per_cpu_init(void)
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{
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/* Disable all interrupts. */
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clear_c0_status(ST0_IM);
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ip30_cpu_time_init();
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#ifdef CONFIG_SMP
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ip30_install_ipi();
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#endif
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enable_percpu_irq(IP30_HEART_L0_IRQ, IRQ_TYPE_NONE);
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enable_percpu_irq(IP30_HEART_L1_IRQ, IRQ_TYPE_NONE);
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enable_percpu_irq(IP30_HEART_L2_IRQ, IRQ_TYPE_NONE);
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enable_percpu_irq(IP30_HEART_ERR_IRQ, IRQ_TYPE_NONE);
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}
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/**
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* plat_mem_setup - despite the name, misc setup happens here.
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*/
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void __init plat_mem_setup(void)
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{
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ip30_mem_init();
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/* XXX: Hard lock on /sbin/init if this flag isn't specified. */
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prom_flags |= PROM_FLAG_DONT_FREE_TEMP;
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#ifdef CONFIG_SMP
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register_smp_ops(&ip30_smp_ops);
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#else
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ip30_per_cpu_init();
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#endif
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ioport_resource.start = 0;
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ioport_resource.end = ~0UL;
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set_io_port_base(IO_BASE);
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}
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