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acrn-kernel/arch/arm/mach-vexpress/spc.h

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treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 174 Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 655 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Richard Fontana <rfontana@redhat.com> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070034.575739538@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-05-27 14:55:21 +08:00
/* SPDX-License-Identifier: GPL-2.0-only */
ARM: vexpress/TC2: add Serial Power Controller (SPC) support The TC2 versatile express core tile integrates a logic block that provides the interface between the dual cluster test-chip and the M3 microcontroller that carries out power management. The logic block, called Serial Power Controller (SPC), contains several memory mapped registers to control among other things low-power states, wake-up irqs and per-CPU jump addresses registers. This patch provides a driver that enables run-time control of features implemented by the SPC power management control logic with an API to be used by different subsystem drivers on top. The SPC control logic is required to be programmed very early in the boot process to reset secondary CPUs on the TC2 testchip, set-up jump addresses and wake-up IRQs for power management. Hence, waiting for core changes to be made in the device core code to enable early registration of platform devices, the driver puts in place an early init scheme that allows kernel drivers to initialize the SPC driver directly from the components requiring it, if their initialization routine is called before this driver init function during the boot process. Device tree bindings documentation for the SPC component is also provided. Cc: Olof Johansson <olof@lixom.net> Cc: Amit Kucheria <amit.kucheria@linaro.org> Cc: Jon Medhurst <tixy@linaro.org> Signed-off-by: Achin Gupta <achin.gupta@arm.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Sudeep KarkadaNagesha <Sudeep.KarkadaNagesha@arm.com> Acked-by: Pawel Moll <pawel.moll@arm.com> [ np: moved from drivers/mfd/ to drivers/platform/vexpress/ ] Signed-off-by: Nicolas Pitre <nico@linaro.org> [ PM: moved again to arch/arm/mach-vexpress, requested by Olof ] [ PM: removed useless printk, from Olof ] [ PM: made the driver SPC-only ] Signed-off-by: Pawel Moll <pawel.moll@arm.com>
2013-07-17 00:05:43 +08:00
/*
*
* Copyright (C) 2012 ARM Limited
*/
#ifndef __SPC_H_
#define __SPC_H_
ARM: vexpress/TC2: add support for CPU DVFS SPC(Serial Power Controller) on TC2 also controls the CPU performance operating points which is essential to provide CPU DVFS. The M3 microcontroller provides two sets of eight performance values, one set for each cluster (CA15 or CA7). Each of this value contains the frequency(kHz) and voltage(mV) at that performance level. It expects these performance level to be passed through the SPC PERF_LVL registers. This patch adds support to populate these performance levels from M3, build the mapping to CPU OPPs at the boot and then use it to get and set the CPU performance level runtime. Signed-off-by: Sudeep KarkadaNagesha <sudeep.karkadanagesha@arm.com> Acked-by: Nicolas Pitre <nico@linaro.org> Acked-by: Pawel Moll <Pawel.Moll@arm.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2013-10-29 20:18:37 +08:00
int __init ve_spc_init(void __iomem *base, u32 a15_clusid, int irq);
ARM: vexpress/TC2: add Serial Power Controller (SPC) support The TC2 versatile express core tile integrates a logic block that provides the interface between the dual cluster test-chip and the M3 microcontroller that carries out power management. The logic block, called Serial Power Controller (SPC), contains several memory mapped registers to control among other things low-power states, wake-up irqs and per-CPU jump addresses registers. This patch provides a driver that enables run-time control of features implemented by the SPC power management control logic with an API to be used by different subsystem drivers on top. The SPC control logic is required to be programmed very early in the boot process to reset secondary CPUs on the TC2 testchip, set-up jump addresses and wake-up IRQs for power management. Hence, waiting for core changes to be made in the device core code to enable early registration of platform devices, the driver puts in place an early init scheme that allows kernel drivers to initialize the SPC driver directly from the components requiring it, if their initialization routine is called before this driver init function during the boot process. Device tree bindings documentation for the SPC component is also provided. Cc: Olof Johansson <olof@lixom.net> Cc: Amit Kucheria <amit.kucheria@linaro.org> Cc: Jon Medhurst <tixy@linaro.org> Signed-off-by: Achin Gupta <achin.gupta@arm.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Sudeep KarkadaNagesha <Sudeep.KarkadaNagesha@arm.com> Acked-by: Pawel Moll <pawel.moll@arm.com> [ np: moved from drivers/mfd/ to drivers/platform/vexpress/ ] Signed-off-by: Nicolas Pitre <nico@linaro.org> [ PM: moved again to arch/arm/mach-vexpress, requested by Olof ] [ PM: removed useless printk, from Olof ] [ PM: made the driver SPC-only ] Signed-off-by: Pawel Moll <pawel.moll@arm.com>
2013-07-17 00:05:43 +08:00
void ve_spc_global_wakeup_irq(bool set);
void ve_spc_cpu_wakeup_irq(u32 cluster, u32 cpu, bool set);
void ve_spc_set_resume_addr(u32 cluster, u32 cpu, u32 addr);
void ve_spc_powerdown(u32 cluster, bool enable);
ARM: vexpress/TC2: Implement MCPM power_down_finish() This patch implements the power_down_finish() method for TC2, to enable the kernel to confirm when CPUs are safely powered down. The information required for determining when a CPU is parked cannot be obtained from any single place, so a few sources of information must be combined: * mcpm_cpu_power_down() must be pending for the CPU, so that we don't get confused by false STANDBYWFI positives arising from CPUidle. This is detected by waiting for the tc2_pm use count for the target CPU to reach 0. * Either the SPC must report that the CPU has asserted STANDBYWFI, or the TC2 tile's reset control logic must be holding the CPU in reset. Just checking for STANDBYWFI is not sufficient, because this signal is not latched when the the cluster is clamped off and powered down: the relevant status bits just drop to zero. This means that STANDBYWFI status cannot be used for reliable detection of the last CPU in a cluster reaching WFI. This patch is required in order for kexec to work with MCPM on TC2. MCPM code was changed in commit 0de0d6467525 ('ARM: 7848/1: mcpm: Implement cpu_kill() to synchronise on powerdown'), and since then it will hit a WARN_ON_ONCE() due to power_down_finish not being implemented on the TC2 platform. Signed-off-by: Dave Martin <Dave.Martin@arm.com> Acked-by: Pawel Moll <pawel.moll@arm.com> Reviewed-by: Nicolas Pitre <nico@linaro.org> Signed-off-by: Olof Johansson <olof@lixom.net>
2013-11-26 00:16:25 +08:00
int ve_spc_cpu_in_wfi(u32 cpu, u32 cluster);
ARM: vexpress/TC2: add Serial Power Controller (SPC) support The TC2 versatile express core tile integrates a logic block that provides the interface between the dual cluster test-chip and the M3 microcontroller that carries out power management. The logic block, called Serial Power Controller (SPC), contains several memory mapped registers to control among other things low-power states, wake-up irqs and per-CPU jump addresses registers. This patch provides a driver that enables run-time control of features implemented by the SPC power management control logic with an API to be used by different subsystem drivers on top. The SPC control logic is required to be programmed very early in the boot process to reset secondary CPUs on the TC2 testchip, set-up jump addresses and wake-up IRQs for power management. Hence, waiting for core changes to be made in the device core code to enable early registration of platform devices, the driver puts in place an early init scheme that allows kernel drivers to initialize the SPC driver directly from the components requiring it, if their initialization routine is called before this driver init function during the boot process. Device tree bindings documentation for the SPC component is also provided. Cc: Olof Johansson <olof@lixom.net> Cc: Amit Kucheria <amit.kucheria@linaro.org> Cc: Jon Medhurst <tixy@linaro.org> Signed-off-by: Achin Gupta <achin.gupta@arm.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Sudeep KarkadaNagesha <Sudeep.KarkadaNagesha@arm.com> Acked-by: Pawel Moll <pawel.moll@arm.com> [ np: moved from drivers/mfd/ to drivers/platform/vexpress/ ] Signed-off-by: Nicolas Pitre <nico@linaro.org> [ PM: moved again to arch/arm/mach-vexpress, requested by Olof ] [ PM: removed useless printk, from Olof ] [ PM: made the driver SPC-only ] Signed-off-by: Pawel Moll <pawel.moll@arm.com>
2013-07-17 00:05:43 +08:00
#endif