2019-05-19 20:07:45 +08:00
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# SPDX-License-Identifier: GPL-2.0-only
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2018-09-05 14:25:06 +08:00
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config CSKY
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def_bool y
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32-bit userspace ABI: introduce ARCH_32BIT_OFF_T config option
All new 32-bit architectures should have 64-bit userspace off_t type, but
existing architectures has 32-bit ones.
To enforce the rule, new config option is added to arch/Kconfig that defaults
ARCH_32BIT_OFF_T to be disabled for new 32-bit architectures. All existing
32-bit architectures enable it explicitly.
New option affects force_o_largefile() behaviour. Namely, if userspace
off_t is 64-bits long, we have no reason to reject user to open big files.
Note that even if architectures has only 64-bit off_t in the kernel
(arc, c6x, h8300, hexagon, nios2, openrisc, and unicore32),
a libc may use 32-bit off_t, and therefore want to limit the file size
to 4GB unless specified differently in the open flags.
Signed-off-by: Yury Norov <ynorov@caviumnetworks.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Yury Norov <ynorov@marvell.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2018-05-16 16:18:49 +08:00
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select ARCH_32BIT_OFF_T
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2019-03-25 22:44:06 +08:00
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select ARCH_HAS_DMA_PREP_COHERENT
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2020-03-10 23:32:56 +08:00
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select ARCH_HAS_GCOV_PROFILE_ALL
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2018-09-05 14:25:06 +08:00
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select ARCH_HAS_SYNC_DMA_FOR_CPU
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select ARCH_HAS_SYNC_DMA_FOR_DEVICE
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select ARCH_USE_BUILTIN_BSWAP
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2020-12-20 16:12:45 +08:00
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select ARCH_USE_QUEUED_RWLOCKS
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2020-05-13 15:15:25 +08:00
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select ARCH_WANT_FRAME_POINTERS if !CPU_CK610
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2020-07-30 20:44:12 +08:00
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select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT
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2018-09-05 14:25:06 +08:00
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select COMMON_CLK
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select CLKSRC_MMIO
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2019-05-10 12:57:27 +08:00
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select CSKY_MPINTC if CPU_CK860
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select CSKY_MP_TIMER if CPU_CK860
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select CSKY_APB_INTC
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2018-11-05 00:47:44 +08:00
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select DMA_DIRECT_REMAP
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2018-09-05 14:25:06 +08:00
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select IRQ_DOMAIN
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select HANDLE_DOMAIN_IRQ
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select DW_APB_TIMER_OF
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2019-08-13 17:41:57 +08:00
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select GENERIC_IOREMAP
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2018-09-05 14:25:06 +08:00
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select GENERIC_LIB_ASHLDI3
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select GENERIC_LIB_ASHRDI3
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select GENERIC_LIB_LSHRDI3
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select GENERIC_LIB_MULDI3
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select GENERIC_LIB_CMPDI2
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select GENERIC_LIB_UCMPDI2
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select GENERIC_ALLOCATOR
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select GENERIC_ATOMIC64
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select GENERIC_CPU_DEVICES
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select GENERIC_IRQ_CHIP
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select GENERIC_IRQ_PROBE
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select GENERIC_IRQ_SHOW
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select GENERIC_IRQ_MULTI_HANDLER
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select GENERIC_SCHED_CLOCK
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select GENERIC_SMP_IDLE_THREAD
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2019-05-10 12:57:27 +08:00
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select GX6605S_TIMER if CPU_CK610
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2018-09-05 14:25:06 +08:00
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select HAVE_ARCH_TRACEHOOK
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2019-03-20 18:27:27 +08:00
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select HAVE_ARCH_AUDITSYSCALL
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2020-07-30 20:44:12 +08:00
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select HAVE_ARCH_MMAP_RND_BITS
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2020-05-26 16:11:52 +08:00
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select HAVE_ARCH_SECCOMP_FILTER
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2020-07-31 17:13:51 +08:00
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select HAVE_CONTEXT_TRACKING
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select HAVE_VIRT_CPU_ACCOUNTING_GEN
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2020-05-13 15:15:25 +08:00
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select HAVE_DEBUG_BUGVERBOSE
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2020-12-24 11:34:43 +08:00
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select HAVE_DEBUG_KMEMLEAK
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2019-03-01 08:50:36 +08:00
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select HAVE_DYNAMIC_FTRACE
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2020-02-18 20:27:39 +08:00
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select HAVE_DYNAMIC_FTRACE_WITH_REGS
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2018-12-09 14:29:59 +08:00
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select HAVE_FUNCTION_TRACER
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2018-12-15 21:04:27 +08:00
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select HAVE_FUNCTION_GRAPH_TRACER
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2020-07-29 00:30:46 +08:00
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select HAVE_FUNCTION_ERROR_INJECTION
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2020-12-20 09:35:09 +08:00
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select HAVE_FUTEX_CMPXCHG if FUTEX && SMP
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2019-03-01 08:50:36 +08:00
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select HAVE_FTRACE_MCOUNT_RECORD
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2018-09-05 14:25:06 +08:00
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select HAVE_KERNEL_GZIP
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select HAVE_KERNEL_LZO
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select HAVE_KERNEL_LZMA
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2020-04-01 09:17:02 +08:00
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select HAVE_KPROBES if !CPU_CK610
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select HAVE_KPROBES_ON_FTRACE if !CPU_CK610
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select HAVE_KRETPROBES if !CPU_CK610
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2019-01-02 22:09:25 +08:00
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select HAVE_PERF_EVENTS
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2019-04-15 17:17:29 +08:00
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select HAVE_PERF_REGS
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select HAVE_PERF_USER_STACK_DUMP
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2018-09-05 14:25:06 +08:00
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select HAVE_DMA_CONTIGUOUS
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2019-12-17 14:57:22 +08:00
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select HAVE_REGS_AND_STACK_ACCESS_API
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2019-11-05 09:58:33 +08:00
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select HAVE_RSEQ
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2019-10-11 10:56:55 +08:00
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select HAVE_STACKPROTECTOR
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2019-03-20 18:27:27 +08:00
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select HAVE_SYSCALL_TRACEPOINTS
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2018-09-05 14:25:06 +08:00
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select MAY_HAVE_SPARSE_IRQ
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select MODULES_USE_ELF_RELA if MODULES
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select OF
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select OF_EARLY_FLATTREE
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2019-01-02 22:09:25 +08:00
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select PERF_USE_VMALLOC if CPU_CK610
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2018-09-05 14:25:06 +08:00
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select RTC_LIB
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select TIMER_OF
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select USB_ARCH_HAS_EHCI
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select USB_ARCH_HAS_OHCI
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2020-01-27 10:56:21 +08:00
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select GENERIC_PCI_IOMAP
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select HAVE_PCI
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select PCI_DOMAINS_GENERIC if PCI
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select PCI_SYSCALL if PCI
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select PCI_MSI if PCI
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2020-09-03 22:22:35 +08:00
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select SET_FS
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2018-09-05 14:25:06 +08:00
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2020-04-02 19:39:42 +08:00
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config LOCKDEP_SUPPORT
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def_bool y
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2020-04-02 19:52:27 +08:00
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config ARCH_SUPPORTS_UPROBES
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def_bool y if !CPU_CK610
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2018-09-05 14:25:06 +08:00
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config CPU_HAS_CACHEV2
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bool
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config CPU_HAS_FPUV2
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bool
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config CPU_HAS_HILO
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bool
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config CPU_HAS_TLBI
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bool
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config CPU_HAS_LDSTEX
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bool
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help
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2020-02-01 09:52:30 +08:00
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For SMP, CPU needs "ldex&stex" instructions for atomic operations.
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2018-09-05 14:25:06 +08:00
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config CPU_NEED_TLBSYNC
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bool
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config CPU_NEED_SOFTALIGN
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bool
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config CPU_NO_USER_BKPT
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bool
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help
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For abiv2 we couldn't use "trap 1" as user space bkpt in gdbserver, because
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abiv2 is 16/32bit instruction set and "trap 1" is 32bit.
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So we need a 16bit instruction as user space bkpt, and it will cause an illegal
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instruction exception.
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In kernel we parse the *regs->pc to determine whether to send SIGTRAP or not.
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config GENERIC_CALIBRATE_DELAY
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def_bool y
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config GENERIC_CSUM
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def_bool y
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config GENERIC_HWEIGHT
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def_bool y
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config MMU
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def_bool y
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2018-12-09 14:18:05 +08:00
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config STACKTRACE_SUPPORT
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def_bool y
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2018-09-05 14:25:06 +08:00
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config TIME_LOW_RES
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def_bool y
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config TRACE_IRQFLAGS_SUPPORT
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def_bool y
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config CPU_TLB_SIZE
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int
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default "128" if (CPU_CK610 || CPU_CK807 || CPU_CK810)
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default "1024" if (CPU_CK860)
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config CPU_ASID_BITS
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int
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default "8" if (CPU_CK610 || CPU_CK807 || CPU_CK810)
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default "12" if (CPU_CK860)
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config L1_CACHE_SHIFT
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int
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default "4" if (CPU_CK610)
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default "5" if (CPU_CK807 || CPU_CK810)
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default "6" if (CPU_CK860)
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2020-07-30 20:44:12 +08:00
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config ARCH_MMAP_RND_BITS_MIN
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default 8
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# max bits determined by the following formula:
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# VA_BITS - PAGE_SHIFT - 3
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config ARCH_MMAP_RND_BITS_MAX
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default 17
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2018-09-05 14:25:06 +08:00
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menu "Processor type and features"
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choice
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prompt "CPU MODEL"
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default CPU_CK807
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config CPU_CK610
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bool "CSKY CPU ck610"
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select CPU_NEED_TLBSYNC
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select CPU_NEED_SOFTALIGN
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select CPU_NO_USER_BKPT
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config CPU_CK810
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bool "CSKY CPU ck810"
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select CPU_HAS_HILO
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select CPU_NEED_TLBSYNC
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config CPU_CK807
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bool "CSKY CPU ck807"
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select CPU_HAS_HILO
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config CPU_CK860
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bool "CSKY CPU ck860"
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select CPU_HAS_TLBI
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select CPU_HAS_CACHEV2
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select CPU_HAS_LDSTEX
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select CPU_HAS_FPUV2
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endchoice
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2019-01-02 22:09:25 +08:00
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choice
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2020-09-07 14:20:18 +08:00
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prompt "PAGE OFFSET"
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default PAGE_OFFSET_80000000
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config PAGE_OFFSET_80000000
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bool "PAGE OFFSET 2G (user:kernel = 2:2)"
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config PAGE_OFFSET_A0000000
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bool "PAGE OFFSET 2.5G (user:kernel = 2.5:1.5)"
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endchoice
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config PAGE_OFFSET
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hex
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default 0x80000000 if PAGE_OFFSET_80000000
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default 0xa0000000 if PAGE_OFFSET_A0000000
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choice
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2019-01-02 22:09:25 +08:00
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prompt "C-SKY PMU type"
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depends on PERF_EVENTS
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depends on CPU_CK807 || CPU_CK810 || CPU_CK860
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config CPU_PMU_NONE
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bool "None"
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config CSKY_PMU_V1
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bool "Performance Monitoring Unit Ver.1"
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endchoice
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2018-09-05 14:25:06 +08:00
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choice
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prompt "Power Manager Instruction (wait/doze/stop)"
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default CPU_PM_NONE
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config CPU_PM_NONE
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bool "None"
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config CPU_PM_WAIT
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bool "wait"
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config CPU_PM_DOZE
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bool "doze"
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config CPU_PM_STOP
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bool "stop"
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endchoice
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csky: Tightly-Coupled Memory or Sram support
The implementation are not only used by TCM but also used by sram on
SOC bus. It follow existed linux tcm software interface, so that old
tcm application codes could be re-used directly.
Software interface list in asm/tcm.h:
- Variables/Const: __tcmdata, __tcmconst
- Functions: __tcmfunc, __tcmlocalfunc
- Malloc/Free: tcm_alloc, tcm_free
In linux menuconfig:
- Choose a TCM contain instrctions + data or separated in ITCM/DTCM.
- Determine TCM_BASE (DTCM_BASE) in phyiscal address.
- Determine size of TCM or ITCM(DTCM) in page counts.
Here is hello tcm example from Documentation/arm/tcm.rst which could
be directly used:
/* Uninitialized data */
static u32 __tcmdata tcmvar;
/* Initialized data */
static u32 __tcmdata tcmassigned = 0x2BADBABEU;
/* Constant */
static const u32 __tcmconst tcmconst = 0xCAFEBABEU;
static void __tcmlocalfunc tcm_to_tcm(void)
{
int i;
for (i = 0; i < 100; i++)
tcmvar ++;
}
static void __tcmfunc hello_tcm(void)
{
/* Some abstract code that runs in ITCM */
int i;
for (i = 0; i < 100; i++) {
tcmvar ++;
}
tcm_to_tcm();
}
static void __init test_tcm(void)
{
u32 *tcmem;
int i;
hello_tcm();
printk("Hello TCM executed from ITCM RAM\n");
printk("TCM variable from testrun: %u @ %p\n", tcmvar, &tcmvar);
tcmvar = 0xDEADBEEFU;
printk("TCM variable: 0x%x @ %p\n", tcmvar, &tcmvar);
printk("TCM assigned variable: 0x%x @ %p\n", tcmassigned, &tcmassigned);
printk("TCM constant: 0x%x @ %p\n", tcmconst, &tcmconst);
/* Allocate some TCM memory from the pool */
tcmem = tcm_alloc(20);
if (tcmem) {
printk("TCM Allocated 20 bytes of TCM @ %p\n", tcmem);
tcmem[0] = 0xDEADBEEFU;
tcmem[1] = 0x2BADBABEU;
tcmem[2] = 0xCAFEBABEU;
tcmem[3] = 0xDEADBEEFU;
tcmem[4] = 0x2BADBABEU;
for (i = 0; i < 5; i++)
printk("TCM tcmem[%d] = %08x\n", i, tcmem[i]);
tcm_free(tcmem, 20);
}
}
TODO:
- Separate fixup mapping from highmem
- Support abiv1
Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
2019-11-27 08:44:33 +08:00
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menuconfig HAVE_TCM
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bool "Tightly-Coupled/Sram Memory"
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select GENERIC_ALLOCATOR
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help
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The implementation are not only used by TCM (Tightly-Coupled Meory)
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but also used by sram on SOC bus. It follow existed linux tcm
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software interface, so that old tcm application codes could be
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re-used directly.
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if HAVE_TCM
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config ITCM_RAM_BASE
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hex "ITCM ram base"
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default 0xffffffff
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config ITCM_NR_PAGES
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int "Page count of ITCM size: NR*4KB"
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range 1 256
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default 32
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config HAVE_DTCM
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bool "DTCM Support"
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config DTCM_RAM_BASE
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hex "DTCM ram base"
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depends on HAVE_DTCM
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default 0xffffffff
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config DTCM_NR_PAGES
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int "Page count of DTCM size: NR*4KB"
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depends on HAVE_DTCM
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range 1 256
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|
|
default 32
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endif
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|
2018-09-05 14:25:06 +08:00
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config CPU_HAS_VDSP
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|
|
bool "CPU has VDSP coprocessor"
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|
|
depends on CPU_HAS_FPU && CPU_HAS_FPUV2
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|
|
config CPU_HAS_FPU
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|
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bool "CPU has FPU coprocessor"
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|
|
|
|
depends on CPU_CK807 || CPU_CK810 || CPU_CK860
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|
|
|
|
2020-01-22 11:15:14 +08:00
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|
|
config CPU_HAS_ICACHE_INS
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|
|
|
|
bool "CPU has Icache invalidate instructions"
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|
|
|
depends on CPU_HAS_CACHEV2
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|
|
|
2018-09-05 14:25:06 +08:00
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|
|
config CPU_HAS_TEE
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|
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|
|
bool "CPU has Trusted Execution Environment"
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|
|
|
|
depends on CPU_CK810
|
|
|
|
|
|
|
|
|
|
config SMP
|
|
|
|
|
bool "Symmetric Multi-Processing (SMP) support for C-SKY"
|
|
|
|
|
depends on CPU_CK860
|
|
|
|
|
default n
|
|
|
|
|
|
|
|
|
|
config NR_CPUS
|
|
|
|
|
int "Maximum number of CPUs (2-32)"
|
|
|
|
|
range 2 32
|
|
|
|
|
depends on SMP
|
2020-07-30 21:12:00 +08:00
|
|
|
default "4"
|
2018-09-05 14:25:06 +08:00
|
|
|
|
|
|
|
|
config HIGHMEM
|
|
|
|
|
bool "High Memory Support"
|
|
|
|
|
depends on !CPU_CK610
|
2020-11-03 17:27:23 +08:00
|
|
|
select KMAP_LOCAL
|
2018-09-05 14:25:06 +08:00
|
|
|
default y
|
|
|
|
|
|
|
|
|
|
config FORCE_MAX_ZONEORDER
|
|
|
|
|
int "Maximum zone order"
|
|
|
|
|
default "11"
|
|
|
|
|
|
|
|
|
|
config RAM_BASE
|
|
|
|
|
hex "DRAM start addr (the same with memory-section in dts)"
|
|
|
|
|
default 0x0
|
|
|
|
|
|
2018-12-19 19:56:14 +08:00
|
|
|
config HOTPLUG_CPU
|
|
|
|
|
bool "Support for hot-pluggable CPUs"
|
|
|
|
|
select GENERIC_IRQ_MIGRATION
|
|
|
|
|
depends on SMP
|
|
|
|
|
help
|
|
|
|
|
Say Y here to allow turning CPUs off and on. CPUs can be
|
|
|
|
|
controlled through /sys/devices/system/cpu/cpu1/hotplug/target.
|
|
|
|
|
|
|
|
|
|
Say N if you want to disable CPU hotplug.
|
2018-09-05 14:25:06 +08:00
|
|
|
endmenu
|
|
|
|
|
|
2020-01-11 13:44:32 +08:00
|
|
|
source "arch/csky/Kconfig.platforms"
|
|
|
|
|
|
2018-09-05 14:25:06 +08:00
|
|
|
source "kernel/Kconfig.hz"
|