2017-11-01 22:08:43 +08:00
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/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
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2006-04-27 07:11:01 +08:00
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#ifndef _LINUX_ELF_EM_H
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#define _LINUX_ELF_EM_H
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/* These constants define the various ELF target machines */
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#define EM_NONE 0
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#define EM_M32 1
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#define EM_SPARC 2
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#define EM_386 3
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#define EM_68K 4
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#define EM_88K 5
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#define EM_486 6 /* Perhaps disused */
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#define EM_860 7
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#define EM_MIPS 8 /* MIPS R3000 (officially, big-endian only) */
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2006-06-30 04:10:50 +08:00
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/* Next two are historical and binaries and
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modules of these types will be rejected by
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Linux. */
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#define EM_MIPS_RS3_LE 10 /* MIPS R3000 little-endian */
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2006-04-27 07:11:01 +08:00
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#define EM_MIPS_RS4_BE 10 /* MIPS R4000 big-endian */
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2006-06-30 04:10:50 +08:00
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2006-04-27 07:11:01 +08:00
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#define EM_PARISC 15 /* HPPA */
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#define EM_SPARC32PLUS 18 /* Sun's "v8plus" */
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#define EM_PPC 20 /* PowerPC */
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2007-07-21 03:39:53 +08:00
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#define EM_PPC64 21 /* PowerPC64 */
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#define EM_SPU 23 /* Cell BE SPU */
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2013-08-28 21:24:53 +08:00
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#define EM_ARM 40 /* ARM 32 bit */
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2006-04-27 07:11:01 +08:00
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#define EM_SH 42 /* SuperH */
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#define EM_SPARCV9 43 /* SPARC v9 64-bit */
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2015-01-28 01:54:39 +08:00
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#define EM_H8_300 46 /* Renesas H8/300 */
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2006-04-27 07:11:01 +08:00
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#define EM_IA_64 50 /* HP/Intel IA-64 */
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#define EM_X86_64 62 /* AMD x86-64 */
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#define EM_S390 22 /* IBM S/390 */
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#define EM_CRIS 76 /* Axis Communications 32-bit embedded processor */
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#define EM_M32R 88 /* Renesas M32R */
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2008-02-08 20:19:31 +08:00
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#define EM_MN10300 89 /* Panasonic/MEI MN10300, AM33 */
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2014-09-27 00:05:39 +08:00
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#define EM_OPENRISC 92 /* OpenRISC 32-bit embedded processor */
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2019-03-18 07:28:39 +08:00
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#define EM_ARCOMPACT 93 /* ARCompact processor */
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2018-12-14 01:23:26 +08:00
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#define EM_XTENSA 94 /* Tensilica Xtensa Architecture */
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blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-07 05:50:22 +08:00
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#define EM_BLACKFIN 106 /* ADI Blackfin Processor */
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2019-03-18 07:30:06 +08:00
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#define EM_UNICORE 110 /* UniCore-32 */
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2014-11-06 15:19:54 +08:00
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#define EM_ALTERA_NIOS2 113 /* Altera Nios II soft-core processor */
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2011-09-28 00:35:21 +08:00
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#define EM_TI_C6000 140 /* TI C6X DSPs */
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2019-03-18 07:29:08 +08:00
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#define EM_HEXAGON 164 /* QUALCOMM Hexagon */
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2019-03-18 07:29:48 +08:00
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#define EM_NDS32 167 /* Andes Technology compact code size
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embedded RISC processor family */
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2013-08-28 21:24:53 +08:00
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#define EM_AARCH64 183 /* ARM 64 bit */
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2015-07-23 02:30:14 +08:00
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#define EM_TILEPRO 188 /* Tilera TILEPro */
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2015-08-18 15:28:01 +08:00
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#define EM_MICROBLAZE 189 /* Xilinx MicroBlaze */
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2015-07-23 02:30:14 +08:00
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#define EM_TILEGX 191 /* Tilera TILE-Gx */
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2019-03-18 07:28:39 +08:00
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#define EM_ARCV2 195 /* ARCv2 Cores */
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2018-06-26 04:23:12 +08:00
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#define EM_RISCV 243 /* RISC-V */
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2016-07-21 02:17:47 +08:00
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#define EM_BPF 247 /* Linux BPF - in-kernel virtual machine */
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2018-12-14 01:22:00 +08:00
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#define EM_CSKY 252 /* C-SKY */
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2022-05-31 18:04:10 +08:00
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#define EM_LOONGARCH 258 /* LoongArch */
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2006-04-27 07:11:01 +08:00
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#define EM_FRV 0x5441 /* Fujitsu FR-V */
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/*
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* This is an interim value that we will use until the committee comes
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* up with a final number.
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*/
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#define EM_ALPHA 0x9026
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/* Bogus old m32r magic number, used by old tools. */
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#define EM_CYGNUS_M32R 0x9041
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/* This is the old interim value for S/390 architecture */
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#define EM_S390_OLD 0xA390
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2008-02-08 20:19:31 +08:00
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/* Also Panasonic/MEI MN10300, AM33 */
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#define EM_CYGNUS_MN10300 0xbeef
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2006-04-27 07:11:01 +08:00
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#endif /* _LINUX_ELF_EM_H */
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