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acrn-kernel/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml

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dt-bindings: PCI: Convert PCIe Host/Endpoint in Cadence platform to DT schema Include Cadence core DT schema and define the Cadence platform DT schema for both Host and Endpoint mode. Note: The Cadence core DT schema could be included for other platforms using Cadence PCIe core. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Rob Herring <robh@kernel.org>
2020-03-05 18:30:16 +08:00
# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/cdns,cdns-pcie-host.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Cadence PCIe host controller
maintainers:
- Tom Joseph <tjoseph@cadence.com>
allOf:
- $ref: /schemas/pci/pci-bus.yaml#
- $ref: "cdns-pcie-host.yaml#"
properties:
compatible:
const: cdns,cdns-pcie-host
reg:
dt-bindings: PCI: cadence: Remove "mem" from reg binding "mem" is not a memory resource and it overlaps with PCIe config space and memory region. Remove "mem" from reg binding. Link: https://lore.kernel.org/r/20200722110317.4744-8-kishon@ti.com Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Rob Herring <robh@kernel.org>
2020-07-22 19:03:09 +08:00
maxItems: 2
dt-bindings: PCI: Convert PCIe Host/Endpoint in Cadence platform to DT schema Include Cadence core DT schema and define the Cadence platform DT schema for both Host and Endpoint mode. Note: The Cadence core DT schema could be included for other platforms using Cadence PCIe core. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Rob Herring <robh@kernel.org>
2020-03-05 18:30:16 +08:00
reg-names:
items:
- const: reg
- const: cfg
msi-parent: true
required:
- reg
- reg-names
dt-bindings: Add missing 'unevaluatedProperties' This doesn't yet do anything in the tools, but make it explicit so we can check either 'unevaluatedProperties' or 'additionalProperties' is present in schemas. 'unevaluatedProperties' is appropriate when including another schema (via '$ref') and all possible properties and/or child nodes are not explicitly listed in the schema with the '$ref'. This is in preparation to add a meta-schema to check for missing 'unevaluatedProperties' or 'additionalProperties'. This has been a constant source of review issues. Acked-by: Mark Brown <broonie@kernel.org> Acked-by: Wolfram Sang <wsa@kernel.org> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-By: Vinod Koul <vkoul@kernel.org> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Ulf Hansson <ulf.hansson@linaro.org> Acked-by: Guenter Roeck <linux@roeck-us.net> Acked-by: Mathieu Poirier <mathieu.poirier@linaro.org> Acked-by: Dmitry Torokhov <dmitry.torokhov@gmail.com> Link: https://lore.kernel.org/r/20201005183830.486085-2-robh@kernel.org Signed-off-by: Rob Herring <robh@kernel.org>
2020-10-06 02:38:27 +08:00
unevaluatedProperties: false
dt-bindings: PCI: Convert PCIe Host/Endpoint in Cadence platform to DT schema Include Cadence core DT schema and define the Cadence platform DT schema for both Host and Endpoint mode. Note: The Cadence core DT schema could be included for other platforms using Cadence PCIe core. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Rob Herring <robh@kernel.org>
2020-03-05 18:30:16 +08:00
examples:
- |
bus {
#address-cells = <2>;
#size-cells = <2>;
pcie@fb000000 {
compatible = "cdns,cdns-pcie-host";
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
bus-range = <0x0 0xff>;
linux,pci-domain = <0>;
vendor-id = <0x17cd>;
device-id = <0x0200>;
reg = <0x0 0xfb000000 0x0 0x01000000>,
dt-bindings: PCI: cadence: Remove "mem" from reg binding "mem" is not a memory resource and it overlaps with PCIe config space and memory region. Remove "mem" from reg binding. Link: https://lore.kernel.org/r/20200722110317.4744-8-kishon@ti.com Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Rob Herring <robh@kernel.org>
2020-07-22 19:03:09 +08:00
<0x0 0x41000000 0x0 0x00001000>;
reg-names = "reg", "cfg";
dt-bindings: PCI: Convert PCIe Host/Endpoint in Cadence platform to DT schema Include Cadence core DT schema and define the Cadence platform DT schema for both Host and Endpoint mode. Note: The Cadence core DT schema could be included for other platforms using Cadence PCIe core. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Rob Herring <robh@kernel.org>
2020-03-05 18:30:16 +08:00
ranges = <0x02000000 0x0 0x42000000 0x0 0x42000000 0x0 0x1000000>,
<0x01000000 0x0 0x43000000 0x0 0x43000000 0x0 0x0010000>;
dt-bindings: PCI: cadence: Deprecate inbound/outbound specific bindings Deprecate cdns,max-outbound-regions and cdns,no-bar-match-nbits for host mode as both these could be derived from "ranges" and "dma-ranges" property. "cdns,max-outbound-regions" property would still be required for EP mode. Link: https://lore.kernel.org/r/20200508130646.23939-2-kishon@ti.com Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Rob Herring <robh@kernel.org> Acked-by: Tom Joseph <tjoseph@cadence.com>
2020-05-08 21:06:43 +08:00
dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x1 0x00000000>;
dt-bindings: PCI: Convert PCIe Host/Endpoint in Cadence platform to DT schema Include Cadence core DT schema and define the Cadence platform DT schema for both Host and Endpoint mode. Note: The Cadence core DT schema could be included for other platforms using Cadence PCIe core. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Rob Herring <robh@kernel.org>
2020-03-05 18:30:16 +08:00
#interrupt-cells = <0x1>;
interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 14 0x1>,
<0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 15 0x1>,
<0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 16 0x1>,
<0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 17 0x1>;
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
msi-parent = <&its_pci>;
phys = <&pcie_phy0>;
phy-names = "pcie-phy";
};
};
...