2014-09-30 22:28:09 +08:00
|
|
|
* Marvell PXA168 Ethernet Controller
|
|
|
|
|
|
|
|
Required properties:
|
|
|
|
- compatible: should be "marvell,pxa168-eth".
|
|
|
|
- reg: address and length of the register set for the device.
|
|
|
|
- interrupts: interrupt for the device.
|
|
|
|
- clocks: pointer to the clock for the device.
|
|
|
|
|
|
|
|
Optional properties:
|
|
|
|
- port-id: Ethernet port number. Should be '0','1' or '2'.
|
|
|
|
- #address-cells: must be 1 when using sub-nodes.
|
|
|
|
- #size-cells: must be 0 when using sub-nodes.
|
|
|
|
- phy-handle: see ethernet.txt file in the same directory.
|
2019-05-03 22:27:07 +08:00
|
|
|
|
|
|
|
The MAC address will be determined using the optional properties
|
|
|
|
defined in ethernet.txt.
|
2014-09-30 22:28:09 +08:00
|
|
|
|
|
|
|
Sub-nodes:
|
|
|
|
Each PHY can be represented as a sub-node. This is not mandatory.
|
|
|
|
|
|
|
|
Sub-nodes required properties:
|
|
|
|
- reg: the MDIO address of the PHY.
|
|
|
|
|
|
|
|
Example:
|
|
|
|
|
|
|
|
eth0: ethernet@f7b90000 {
|
|
|
|
compatible = "marvell,pxa168-eth";
|
|
|
|
reg = <0xf7b90000 0x10000>;
|
|
|
|
clocks = <&chip CLKID_GETH0>;
|
|
|
|
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
#address-cells = <1>;
|
|
|
|
#size-cells = <0>;
|
|
|
|
phy-handle = <ðphy0>;
|
|
|
|
|
|
|
|
ethphy0: ethernet-phy@0 {
|
|
|
|
reg = <0>;
|
|
|
|
};
|
|
|
|
};
|