2019-10-24 18:18:29 +08:00
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef __IP30_COMMON_H
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#define __IP30_COMMON_H
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2020-09-21 04:51:50 +08:00
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/*
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* Power Switch is wired via BaseIO BRIDGE slot #6.
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*
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* ACFail is wired via BaseIO BRIDGE slot #7.
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*/
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#define IP30_POWER_IRQ HEART_L2_INT_POWER_BTN
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#define IP30_HEART_L0_IRQ (MIPS_CPU_IRQ_BASE + 2)
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#define IP30_HEART_L1_IRQ (MIPS_CPU_IRQ_BASE + 3)
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#define IP30_HEART_L2_IRQ (MIPS_CPU_IRQ_BASE + 4)
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#define IP30_HEART_TIMER_IRQ (MIPS_CPU_IRQ_BASE + 5)
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#define IP30_HEART_ERR_IRQ (MIPS_CPU_IRQ_BASE + 6)
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extern void __init ip30_install_ipi(void);
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2019-10-24 18:18:29 +08:00
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extern struct plat_smp_ops ip30_smp_ops;
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extern void __init ip30_per_cpu_init(void);
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#endif /* __IP30_COMMON_H */
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