acrn-kernel/arch/x86/events/Makefile

# SPDX-License-Identifier: GPL-2.0-only
obj-y					+= core.o probe.o utils.o
obj-$(CONFIG_PERF_EVENTS_INTEL_RAPL)	+= rapl.o
obj-y					+= amd/
obj-$(CONFIG_X86_LOCAL_APIC)            += msr.o
obj-$(CONFIG_CPU_SUP_INTEL)		+= intel/
obj-$(CONFIG_CPU_SUP_CENTAUR)		+= zhaoxin/
obj-$(CONFIG_CPU_SUP_ZHAOXIN)		+= zhaoxin/
treewide: Add SPDX license identifier - Makefile/Kconfig Add SPDX license identifiers to all Make/Kconfig files which: - Have no license information of any form These files fall under the project license, GPL v2 only. The resulting SPDX license identifier is: GPL-2.0-only Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> 2019-05-19 20:07:45 +08:00			`# SPDX-License-Identifier: GPL-2.0-only`
perf/x86: Move branch classifier Commit 3e702ff6d1ea ("perf/x86: Add LBR software filter support for Intel CPUs") introduces a software branch filter which complements the hardware branch filter and adds an x86 branch classifier. Move the branch classifier to arch/x86/events/ so that it can be utilized by other vendors for branch record filtering. Signed-off-by: Sandipan Das <sandipan.das@amd.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Link: https://lore.kernel.org/r/bae5b95470d6bd49f40954bd379f414f5afcb965.1660211399.git.sandipan.das@amd.com 2022-08-11 20:29:56 +08:00			`obj-y += core.o probe.o utils.o`
perf/x86/rapl: Fix RAPL config variable bug This patch fixes a bug introduced by: fd3ae1e1587d6 ("perf/x86/rapl: Move RAPL support to common x86 code") The Kconfig variable name was wrong. It was missing the CONFIG_ prefix. Signed-off-by: Stephane Eranian <eraniangoogle.com> Signed-off-by: Ingo Molnar <mingo@kernel.org> Tested-by: Kim Phillips <kim.phillips@amd.com> Acked-by: Peter Zijlstra <peterz@infradead.org> Link: https://lore.kernel.org/r/20200528201614.250182-1-eranian@google.com 2020-05-29 04:16:14 +08:00			`obj-$(CONFIG_PERF_EVENTS_INTEL_RAPL) += rapl.o`
perf/x86/events: Add an AMD-specific Makefile Move the AMD pieces from the generic Makefile so that $ make arch/x86/events/amd/<file>.s can work too. Otherwise you get: $ make arch/x86/events/amd/ibs.s scripts/Makefile.build:44: arch/x86/events/amd/Makefile: No such file or directory make[1]: * No rule to make target 'arch/x86/events/amd/Makefile'. Stop. Makefile:1636: recipe for target 'arch/x86/events/amd/ibs.s' failed make: * [arch/x86/events/amd/ibs.s] Error 2 Signed-off-by: Borislav Petkov <bp@suse.de> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Arnaldo Carvalho de Melo <acme@redhat.com> Cc: Jiri Olsa <jolsa@redhat.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Stephane Eranian <eranian@google.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Vince Weaver <vincent.weaver@maine.edu> Link: http://lkml.kernel.org/r/20170126080819.417-1-bp@alien8.de Signed-off-by: Ingo Molnar <mingo@kernel.org> 2017-01-26 16:08:19 +08:00			`obj-y += amd/`
			`obj-$(CONFIG_X86_LOCAL_APIC) += msr.o`
x86/perf/intel/uncore: Make the Intel uncore PMU driver modular By default, the uncore driver will be built into the kernel. If it is configured as a module, the supported CPU model can be auto loaded. This patch also cleans up the code of uncore_cpu_init() and uncore_pci_init(). Based-on-a-patch-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Kan Liang <kan.liang@intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Arnaldo Carvalho de Melo <acme@redhat.com> Cc: Jiri Olsa <jolsa@redhat.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Stephane Eranian <eranian@google.com> Cc: Vince Weaver <vincent.weaver@maine.edu> Link: http://lkml.kernel.org/r/1458462817-2475-1-git-send-email-kan.liang@intel.com Signed-off-by: Ingo Molnar <mingo@kernel.org> 2016-03-20 16:33:36 +08:00			`obj-$(CONFIG_CPU_SUP_INTEL) += intel/`
x86/perf: Add hardware performance events support for Zhaoxin CPU. Zhaoxin CPU has provided facilities for monitoring performance via PMU (Performance Monitor Unit), but the functionality is unused so far. Therefore, add support for zhaoxin pmu to make performance related hardware events available. The PMU is mostly an Intel Architectural PerfMon-v2 with a novel errata for the ZXC line. It supports the following events: ----------------------------------------------------------------------------------------------------------------------------------- Event \| Event \| Umask \| Description \| Select \| \| ----------------------------------------------------------------------------------------------------------------------------------- cpu-cycles \| 82h \| 00h \| unhalt core clock instructions \| 00h \| 00h \| number of instructions at retirement. cache-references \| 15h \| 05h \| number of fillq pushs at the current cycle. cache-misses \| 1ah \| 05h \| number of l2 miss pushed by fillq. branch-instructions \| 28h \| 00h \| counts the number of branch instructions retired. branch-misses \| 29h \| 00h \| mispredicted branch instructions at retirement. bus-cycles \| 83h \| 00h \| unhalt bus clock stalled-cycles-frontend \| 01h \| 01h \| Increments each cycle the # of Uops issued by the RAT to RS. stalled-cycles-backend \| 0fh \| 04h \| RS0/1/2/3/45 empty L1-dcache-loads \| 68h \| 05h \| number of retire/commit load. L1-dcache-load-misses \| 4bh \| 05h \| retired load uops whose data source followed an L1 miss. L1-dcache-stores \| 69h \| 06h \| number of retire/commit Store,no LEA L1-dcache-store-misses \| 62h \| 05h \| cache lines in M state evicted out of L1D due to Snoop HitM or dirty line replacement. L1-icache-loads \| 00h \| 03h \| number of l1i cache access for valid normal fetch,including un-cacheable access. L1-icache-load-misses \| 01h \| 03h \| number of l1i cache miss for valid normal fetch,including un-cacheable miss. L1-icache-prefetches \| 0ah \| 03h \| number of prefetch. L1-icache-prefetch-misses \| 0bh \| 03h \| number of prefetch miss. dTLB-loads \| 68h \| 05h \| number of retire/commit load dTLB-load-misses \| 2ch \| 05h \| number of load operations miss all level tlbs and cause a tablewalk. dTLB-stores \| 69h \| 06h \| number of retire/commit Store,no LEA dTLB-store-misses \| 30h \| 05h \| number of store operations miss all level tlbs and cause a tablewalk. dTLB-prefetches \| 64h \| 05h \| number of hardware pte prefetch requests dispatched out of the prefetch FIFO. dTLB-prefetch-misses \| 65h \| 05h \| number of hardware pte prefetch requests miss the l1d data cache. iTLB-load \| 00h \| 00h \| actually counter instructions. iTLB-load-misses \| 34h \| 05h \| number of code operations miss all level tlbs and cause a tablewalk. ----------------------------------------------------------------------------------------------------------------------------------- Reported-by: kbuild test robot <lkp@intel.com> Signed-off-by: CodyYao-oc <CodyYao-oc@zhaoxin.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Link: https://lkml.kernel.org/r/1586747669-4827-1-git-send-email-CodyYao-oc@zhaoxin.com 2020-04-13 11:14:29 +08:00			`obj-$(CONFIG_CPU_SUP_CENTAUR) += zhaoxin/`
			`obj-$(CONFIG_CPU_SUP_ZHAOXIN) += zhaoxin/`