90 lines
2.6 KiB
C
90 lines
2.6 KiB
C
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/*
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* linux/arch/sh/boards/se/7780/irq.c
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*
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* Copyright (C) 2006,2007 Nobuhiro Iwamatsu
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*
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* Hitachi UL SolutionEngine 7780 Support.
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <linux/interrupt.h>
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#include <asm/irq.h>
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#include <asm/io.h>
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#include <asm/se7780.h>
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#define INTC_INTMSK0 0xFFD00044
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#define INTC_INTMSKCLR0 0xFFD00064
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static void disable_se7780_irq(unsigned int irq)
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{
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struct intc2_data *p = get_irq_chip_data(irq);
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ctrl_outl(1 << p->msk_shift, INTC_INTMSK0 + p->msk_offset);
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}
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static void enable_se7780_irq(unsigned int irq)
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{
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struct intc2_data *p = get_irq_chip_data(irq);
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ctrl_outl(1 << p->msk_shift, INTC_INTMSKCLR0 + p->msk_offset);
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}
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static struct irq_chip se7780_irq_chip __read_mostly = {
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.name = "SE7780",
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.mask = disable_se7780_irq,
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.unmask = enable_se7780_irq,
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.mask_ack = disable_se7780_irq,
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};
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static struct intc2_data intc2_irq_table[] = {
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{ 2, 0, 31, 0, 31, 3 }, /* daughter board EXTINT1 */
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{ 4, 0, 30, 0, 30, 3 }, /* daughter board EXTINT2 */
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{ 6, 0, 29, 0, 29, 3 }, /* daughter board EXTINT3 */
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{ 8, 0, 28, 0, 28, 3 }, /* SMC 91C111 (LAN) */
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{ 10, 0, 27, 0, 27, 3 }, /* daughter board EXTINT4 */
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{ 4, 0, 30, 0, 30, 3 }, /* daughter board EXTINT5 */
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{ 2, 0, 31, 0, 31, 3 }, /* daughter board EXTINT6 */
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{ 2, 0, 31, 0, 31, 3 }, /* daughter board EXTINT7 */
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{ 2, 0, 31, 0, 31, 3 }, /* daughter board EXTINT8 */
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{ 0 , 0, 24, 0, 24, 3 }, /* SM501 */
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};
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/*
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* Initialize IRQ setting
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*/
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void __init init_se7780_IRQ(void)
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{
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int i ;
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/* enable all interrupt at FPGA */
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ctrl_outw(0, FPGA_INTMSK1);
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/* mask SM501 interrupt */
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ctrl_outw((ctrl_inw(FPGA_INTMSK1) | 0x0002), FPGA_INTMSK1);
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/* enable all interrupt at FPGA */
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ctrl_outw(0, FPGA_INTMSK2);
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/* set FPGA INTSEL register */
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/* FPGA + 0x06 */
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ctrl_outw( ((IRQPIN_SM501 << IRQPOS_SM501) |
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(IRQPIN_SMC91CX << IRQPOS_SMC91CX)), FPGA_INTSEL1);
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/* FPGA + 0x08 */
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ctrl_outw(((IRQPIN_EXTINT4 << IRQPOS_EXTINT4) |
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(IRQPIN_EXTINT3 << IRQPOS_EXTINT3) |
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(IRQPIN_EXTINT2 << IRQPOS_EXTINT2) |
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(IRQPIN_EXTINT1 << IRQPOS_EXTINT1)), FPGA_INTSEL2);
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/* FPGA + 0x0A */
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ctrl_outw((IRQPIN_PCCPW << IRQPOS_PCCPW), FPGA_INTSEL3);
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for (i = 0; i < ARRAY_SIZE(intc2_irq_table); i++) {
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disable_irq_nosync(intc2_irq_table[i].irq);
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set_irq_chip_and_handler_name( intc2_irq_table[i].irq, &se7780_irq_chip,
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handle_level_irq, "level");
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set_irq_chip_data( intc2_irq_table[i].irq, &intc2_irq_table[i] );
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disable_se7780_irq(intc2_irq_table[i].irq);
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}
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}
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