316 lines
7.3 KiB
C
316 lines
7.3 KiB
C
/*
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* Copyright (C) 2018 Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <types.h>
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#include <spinlock.h>
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#include <pci.h>
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#include <pgtable.h>
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#include <uart16550.h>
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#include <io.h>
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#include <mmu.h>
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#define MAX_BDF_LEN 8
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struct console_uart {
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bool enabled;
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bool serial_port_mapped;
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union {
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uint16_t port_address;
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void *mmio_base_vaddr;
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};
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spinlock_t rx_lock;
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spinlock_t tx_lock;
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};
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#if defined(CONFIG_SERIAL_PIO_BASE)
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static struct console_uart uart = {
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.enabled = true,
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.serial_port_mapped = true,
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.port_address = CONFIG_SERIAL_PIO_BASE,
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};
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static char pci_bdf_info[MAX_BDF_LEN + 1U];
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#elif defined(CONFIG_SERIAL_PCI_BDF)
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static struct console_uart uart = {
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.enabled = true,
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};
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static char pci_bdf_info[MAX_BDF_LEN + 1U] = CONFIG_SERIAL_PCI_BDF;
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#else
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static struct console_uart uart;
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static char pci_bdf_info[MAX_BDF_LEN + 1U];
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#endif
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typedef uint32_t uart_reg_t;
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static union pci_bdf serial_pci_bdf;
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static uint32_t pci_direct_calc_address(union pci_bdf bdf, uint32_t offset)
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{
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uint32_t addr = (uint32_t)bdf.value;
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addr <<= 8U;
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addr |= (offset | PCI_CFG_ENABLE);
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return addr;
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}
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static uint32_t pci_direct_read_cfg(union pci_bdf bdf, uint32_t offset, uint32_t bytes)
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{
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uint32_t addr;
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uint32_t val;
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addr = pci_direct_calc_address(bdf, offset);
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/* Write address to ADDRESS register */
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pio_write32(addr, (uint16_t)PCI_CONFIG_ADDR);
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/* Read result from DATA register */
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switch (bytes) {
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case 1U:
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val = (uint32_t)pio_read8((uint16_t)PCI_CONFIG_DATA + ((uint16_t)offset & 3U));
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break;
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case 2U:
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val = (uint32_t)pio_read16((uint16_t)PCI_CONFIG_DATA + ((uint16_t)offset & 2U));
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break;
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default:
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val = pio_read32((uint16_t)PCI_CONFIG_DATA);
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break;
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}
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return val;
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}
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static void pci_direct_write_cfg(union pci_bdf bdf, uint32_t offset, uint32_t bytes, uint32_t val)
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{
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uint32_t addr = pci_direct_calc_address(bdf, offset);
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/* Write address to ADDRESS register */
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pio_write32(addr, (uint16_t)PCI_CONFIG_ADDR);
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/* Write value to DATA register */
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switch (bytes) {
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case 1U:
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pio_write8((uint8_t)val, (uint16_t)PCI_CONFIG_DATA + ((uint16_t)offset & 3U));
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break;
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case 2U:
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pio_write16((uint16_t)val, (uint16_t)PCI_CONFIG_DATA + ((uint16_t)offset & 2U));
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break;
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default:
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pio_write32(val, (uint16_t)PCI_CONFIG_DATA);
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break;
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}
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}
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struct pci_cfg_ops pci_direct_cfg_ops = {
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.pci_read_cfg = pci_direct_read_cfg,
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.pci_write_cfg = pci_direct_write_cfg,
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};
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/* PCI BDF must follow format: bus:dev.func, for example 0:18.2 */
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static uint16_t get_pci_bdf_value(char *bdf)
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{
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char *pos;
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char *start = bdf;
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char dst[3][4];
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uint64_t value= 0UL;
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pos = strchr(start, ':');
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if (pos != NULL) {
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strncpy_s(dst[0], 3, start, pos -start);
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start = pos + 1;
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pos = strchr(start, '.');
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if (pos != NULL) {
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strncpy_s(dst[1], 3, start, pos -start);
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start = pos + 1;
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strncpy_s(dst[2], 2, start, 1);
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value= (strtoul_hex(dst[0]) << 8) | (strtoul_hex(dst[1]) << 3) | strtoul_hex(dst[2]);
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}
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}
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return (uint16_t)value;
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}
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/**
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* @pre uart->enabled == true
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*/
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static inline uint32_t uart16550_read_reg(struct console_uart uart, uint16_t reg_idx)
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{
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if (uart.serial_port_mapped) {
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return pio_read8(uart.port_address + reg_idx);
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} else {
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return mmio_read32((uint32_t *)uart.mmio_base_vaddr + reg_idx);
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}
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}
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/**
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* @pre uart->enabled == true
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*/
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static inline void uart16550_write_reg(struct console_uart uart, uint32_t val, uint16_t reg_idx)
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{
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if (uart.serial_port_mapped) {
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pio_write8(val, uart.port_address + reg_idx);
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} else {
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mmio_write32(val, (uint32_t *)uart.mmio_base_vaddr + reg_idx);
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}
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}
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static void uart16550_calc_baud_div(uint32_t ref_freq, uint32_t *baud_div_ptr, uint32_t baud_rate_arg)
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{
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uint32_t baud_rate = baud_rate_arg;
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uint32_t baud_multiplier = baud_rate < BAUD_460800 ? 16U : 13U;
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if (baud_rate == 0U) {
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baud_rate = BAUD_115200;
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}
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*baud_div_ptr = ref_freq / (baud_multiplier * baud_rate);
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}
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/**
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* @pre uart->enabled == true
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*/
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static void uart16550_set_baud_rate(uint32_t baud_rate)
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{
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uint32_t baud_div, duart_clock = UART_CLOCK_RATE;
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uart_reg_t temp_reg;
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/* Calculate baud divisor */
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uart16550_calc_baud_div(duart_clock, &baud_div, baud_rate);
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/* Enable DLL and DLM registers for setting the Divisor */
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temp_reg = uart16550_read_reg(uart, UART16550_LCR);
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temp_reg |= LCR_DLAB;
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uart16550_write_reg(uart, temp_reg, UART16550_LCR);
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/* Write the appropriate divisor value */
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uart16550_write_reg(uart, ((baud_div >> 8U) & 0xFFU), UART16550_DLM);
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uart16550_write_reg(uart, (baud_div & 0xFFU), UART16550_DLL);
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/* Disable DLL and DLM registers */
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temp_reg &= ~LCR_DLAB;
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uart16550_write_reg(uart, temp_reg, UART16550_LCR);
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}
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void uart16550_init(bool early_boot)
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{
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if (!uart.enabled) {
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return;
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}
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if (!early_boot && !uart.serial_port_mapped) {
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uart.mmio_base_vaddr = hpa2hva(hva2hpa_early(uart.mmio_base_vaddr));
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hv_access_memory_region_update((uint64_t)uart.mmio_base_vaddr, PDE_SIZE);
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return;
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}
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/* if configure serial PCI BDF, get its base MMIO address */
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if (!uart.serial_port_mapped) {
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serial_pci_bdf.value = get_pci_bdf_value(pci_bdf_info);
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uart.mmio_base_vaddr =
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hpa2hva_early(pci_pdev_read_cfg(serial_pci_bdf, pci_bar_offset(0), 4U) & PCIM_BAR_MEM_BASE);
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}
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spinlock_init(&uart.rx_lock);
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spinlock_init(&uart.tx_lock);
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/* Enable TX and RX FIFOs */
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uart16550_write_reg(uart, FCR_FIFOE | FCR_RFR | FCR_TFR, UART16550_FCR);
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/* Set-up data bits / parity / stop bits. */
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uart16550_write_reg(uart, (LCR_WL8 | LCR_NB_STOP_BITS_1 | LCR_PARITY_NONE), UART16550_LCR);
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/* Disable interrupts (we use polling) */
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uart16550_write_reg(uart, UART_IER_DISABLE_ALL, UART16550_IER);
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/* Set baud rate */
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uart16550_set_baud_rate(BAUD_115200);
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/* Data terminal ready + Request to send */
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uart16550_write_reg(uart, MCR_RTS | MCR_DTR, UART16550_MCR);
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}
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char uart16550_getc(void)
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{
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char ret = -1;
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if (!uart.enabled) {
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return ret;
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}
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spinlock_obtain(&uart.rx_lock);
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/* If a character has been received, read it */
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if ((uart16550_read_reg(uart, UART16550_LSR) & LSR_DR) == LSR_DR) {
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/* Read a character */
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ret = uart16550_read_reg(uart, UART16550_RBR);
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}
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spinlock_release(&uart.rx_lock);
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return ret;
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}
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/**
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* @pre uart->enabled == true
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*/
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static void uart16550_putc(char c)
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{
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uint8_t temp;
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uint32_t reg;
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/* Ensure there are no further Transmit buffer write requests */
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do {
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reg = uart16550_read_reg(uart, UART16550_LSR);
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} while ((reg & LSR_THRE) == 0U || (reg & LSR_TEMT) == 0U);
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temp = (uint8_t)c;
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/* Transmit the character. */
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uart16550_write_reg(uart, (uint32_t)temp, UART16550_THR);
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}
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size_t uart16550_puts(const char *buf, uint32_t len)
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{
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uint32_t i;
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if (!uart.enabled) {
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return len;
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}
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spinlock_obtain(&uart.tx_lock);
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for (i = 0U; i < len; i++) {
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/* Transmit character */
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uart16550_putc(*buf);
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if (*buf == '\n') {
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/* Append '\r', no need change the len */
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uart16550_putc('\r');
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}
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buf++;
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}
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spinlock_release(&uart.tx_lock);
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return len;
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}
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void uart16550_set_property(bool enabled, bool port_mapped, uint64_t base_addr)
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{
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uart.enabled = enabled;
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uart.serial_port_mapped = port_mapped;
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if (port_mapped) {
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uart.port_address = base_addr;
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} else {
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const char *bdf = (const char *)base_addr;
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strncpy_s(pci_bdf_info, MAX_BDF_LEN + 1U, bdf, MAX_BDF_LEN);
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}
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}
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bool is_pci_dbg_uart(union pci_bdf bdf_value)
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{
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bool ret = false;
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if (uart.enabled && !uart.serial_port_mapped) {
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if (bdf_value.value == serial_pci_bdf.value) {
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ret = true;
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}
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}
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return ret;
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}
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