197 lines
3.8 KiB
C
197 lines
3.8 KiB
C
/*
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* Copyright (C) 2018-2022 Intel Corporation.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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* this file contains pure vmx operations
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*/
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#include <types.h>
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#include <asm/msr.h>
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#include <asm/per_cpu.h>
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#include <asm/pgtable.h>
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#include <asm/vmx.h>
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/**
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* @pre addr != NULL && addr is 4KB-aligned
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* rev[31:0] 32 bits located at vmxon region physical address
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* @pre rev[30:0] == VMCS revision && rev[31] == 0
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*/
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static inline void exec_vmxon(void *addr)
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{
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/* Turn VMX on, pre-conditions can avoid VMfailInvalid
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* here no need check RFLAGS since it will generate #GP or #UD
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* except VMsuccess. SDM 30.3
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*/
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asm volatile (
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"vmxon (%%rax)\n"
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:
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: "a"(addr)
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: "cc", "memory");
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}
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/* Per cpu data to hold the vmxon_region for each pcpu.
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* It will be used again when we start a pcpu after the pcpu was down.
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* S3 enter/exit will use it.
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* Only run on current pcpu.
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*/
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void vmx_on(void)
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{
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uint64_t tmp64;
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uint32_t tmp32;
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void *vmxon_region_va = (void *)get_cpu_var(vmxon_region);
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uint64_t vmxon_region_pa;
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/* Initialize vmxon page with revision id from IA32 VMX BASIC MSR */
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tmp32 = (uint32_t)msr_read(MSR_IA32_VMX_BASIC);
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(void)memcpy_s(vmxon_region_va, 4U, (void *)&tmp32, 4U);
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/* Turn on CR0.NE and CR4.VMXE */
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CPU_CR_READ(cr0, &tmp64);
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CPU_CR_WRITE(cr0, tmp64 | CR0_NE);
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CPU_CR_READ(cr4, &tmp64);
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CPU_CR_WRITE(cr4, tmp64 | CR4_VMXE);
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/* Read Feature ControL MSR */
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tmp64 = msr_read(MSR_IA32_FEATURE_CONTROL);
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/* Check if feature control is locked */
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if ((tmp64 & MSR_IA32_FEATURE_CONTROL_LOCK) == 0U) {
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/* Lock and enable VMX support */
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tmp64 |= (MSR_IA32_FEATURE_CONTROL_LOCK |
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MSR_IA32_FEATURE_CONTROL_VMX_NO_SMX);
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msr_write(MSR_IA32_FEATURE_CONTROL, tmp64);
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}
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/* Turn ON VMX */
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vmxon_region_pa = hva2hpa(vmxon_region_va);
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exec_vmxon(&vmxon_region_pa);
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}
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static inline void exec_vmxoff(void)
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{
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asm volatile ("vmxoff" : : : "memory");
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}
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/**
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* @pre addr != NULL && addr is 4KB-aligned
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* @pre addr != VMXON pointer
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*/
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void exec_vmclear(void *addr)
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{
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/* pre-conditions can avoid VMfail
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* here no need check RFLAGS since it will generate #GP or #UD
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* except VMsuccess. SDM 30.3
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*/
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asm volatile (
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"vmclear (%%rax)\n"
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:
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: "a"(addr)
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: "cc", "memory");
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}
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/**
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* @pre addr != NULL && addr is 4KB-aligned
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* @pre addr != VMXON pointer
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*/
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void exec_vmptrld(void *addr)
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{
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/* pre-conditions can avoid VMfail
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* here no need check RFLAGS since it will generate #GP or #UD
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* except VMsuccess. SDM 30.3
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*/
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asm volatile (
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"vmptrld (%%rax)\n"
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:
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: "a"(addr)
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: "cc", "memory");
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}
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/*
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* @pre vcpu != NULL
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*/
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void load_va_vmcs(const uint8_t *vmcs_va)
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{
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uint64_t vmcs_pa;
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vmcs_pa = hva2hpa(vmcs_va);
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exec_vmptrld((void *)&vmcs_pa);
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}
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/*
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* @pre vcpu != NULL
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*/
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void clear_va_vmcs(const uint8_t *vmcs_va)
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{
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uint64_t vmcs_pa;
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vmcs_pa = hva2hpa(vmcs_va);
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exec_vmclear((void *)&vmcs_pa);
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}
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/**
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* only run on current pcpu
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*/
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void vmx_off(void)
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{
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void **vmcs_ptr = &get_cpu_var(vmcs_run);
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if (*vmcs_ptr != NULL) {
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clear_va_vmcs(*vmcs_ptr);
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*vmcs_ptr = NULL;
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}
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exec_vmxoff();
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}
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uint64_t exec_vmread64(uint32_t field_full)
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{
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uint64_t value;
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asm volatile (
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"vmread %%rdx, %%rax "
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: "=a" (value)
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: "d"(field_full)
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: "cc");
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return value;
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}
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uint32_t exec_vmread32(uint32_t field)
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{
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uint64_t value;
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value = exec_vmread64(field);
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return (uint32_t)value;
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}
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uint16_t exec_vmread16(uint32_t field)
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{
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uint64_t value;
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value = exec_vmread64(field);
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return (uint16_t)value;
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}
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void exec_vmwrite64(uint32_t field_full, uint64_t value)
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{
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asm volatile (
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"vmwrite %%rax, %%rdx "
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: : "a" (value), "d"(field_full)
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: "cc");
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}
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void exec_vmwrite32(uint32_t field, uint32_t value)
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{
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exec_vmwrite64(field, (uint64_t)value);
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}
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void exec_vmwrite16(uint32_t field, uint16_t value)
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{
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exec_vmwrite64(field, (uint64_t)value);
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}
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