130 lines
3.5 KiB
C
130 lines
3.5 KiB
C
/*
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* Copyright (C) 2019 Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <types.h>
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#include <errno.h>
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#include <asm/cpufeatures.h>
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#include <asm/cpu_caps.h>
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#include <asm/sgx.h>
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#include <asm/cpuid.h>
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#include <asm/guest/vm.h>
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#include <logmsg.h>
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#define SGX_OPTED_IN (MSR_IA32_FEATURE_CONTROL_SGX_GE | MSR_IA32_FEATURE_CONTROL_LOCK)
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/* For the static variables, which are not explicitly initialzed will be inited to 0 */
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static int32_t init_sgx_ret = 0;
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static struct epc_section pepc_sections[MAX_EPC_SECTIONS]; /* physcial epc sections */
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static struct epc_map vm_epc_maps[MAX_EPC_SECTIONS][CONFIG_MAX_VM_NUM]; /* epc resource mapping for VMs */
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static int32_t get_epc_section(uint32_t sec_id, uint64_t* base, uint64_t* size)
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{
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uint32_t eax = 0U, ebx = 0U, ecx = 0U, edx = 0U, type;
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int32_t ret = 0;
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cpuid_subleaf(CPUID_SGX_LEAF, sec_id + CPUID_SGX_EPC_SUBLEAF_BASE, &eax, &ebx, &ecx, &edx);
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type = eax & CPUID_SGX_EPC_TYPE_MASK;
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if (type == CPUID_SGX_EPC_TYPE_VALID) {
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*base = (((uint64_t)ebx & CPUID_SGX_EPC_HIGH_MASK) << 32U) |
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((uint64_t)eax & CPUID_SGX_EPC_LOW_MASK);
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*size = (((uint64_t)edx & CPUID_SGX_EPC_HIGH_MASK) << 32U) |
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((uint64_t)ecx & CPUID_SGX_EPC_LOW_MASK);
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if (*size != 0UL) {
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pepc_sections[sec_id].base = *base;
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pepc_sections[sec_id].size = *size;
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} else {
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ret = -EINVAL;
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}
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} else if (type == CPUID_SGX_EPC_TYPE_INVALID) {
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/* indicate the end of epc enumeration */
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} else {
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pr_err("%s: unsupport EPC type %u", __func__, type);
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ret = -EINVAL;
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}
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return ret;
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}
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/* Enumerate physcial EPC resource and partition it according to VM configurations.
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* Build the mappings between HPA and GPA for EPT mapping later.
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* EPC resource partition and mapping relationship will stay unchanged after sgx init.
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*/
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static int32_t partition_epc(void)
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{
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uint16_t vm_id = 0U;
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uint32_t psec_id = 0U, mid = 0U;
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uint64_t psec_addr = 0UL, psec_size = 0UL;
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uint64_t vm_request_size = 0UL, free_size = 0UL, alloc_size;
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struct acrn_vm_config *vm_config;
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int32_t ret = 0;
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while ((psec_id < MAX_EPC_SECTIONS) && (vm_id < CONFIG_MAX_VM_NUM)) {
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if (vm_request_size == 0U) {
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mid = 0U;
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vm_config = get_vm_config(vm_id);
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vm_request_size = vm_config->epc.size;
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}
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if ((free_size == 0UL) && (vm_request_size != 0UL)) {
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ret = get_epc_section(psec_id, &psec_addr, &psec_size);
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free_size = psec_size;
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if ((ret != 0) || (free_size == 0UL)) {
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break;
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}
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psec_id++;
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}
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if (vm_request_size != 0UL) {
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if (vm_request_size <= free_size) {
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alloc_size = vm_request_size;
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} else {
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alloc_size = free_size;
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}
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vm_epc_maps[mid][vm_id].size = alloc_size;
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vm_epc_maps[mid][vm_id].hpa = psec_addr + psec_size - free_size;
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vm_epc_maps[mid][vm_id].gpa = vm_config->epc.base + vm_config->epc.size - vm_request_size;
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vm_request_size -= alloc_size;
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free_size -= alloc_size;
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mid++;
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}
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if (vm_request_size == 0UL) {
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vm_id++;
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}
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}
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if (vm_request_size != 0UL) {
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ret = -ENOMEM;
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}
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return ret;
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}
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struct epc_section* get_phys_epc(void)
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{
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return pepc_sections;
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}
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struct epc_map* get_epc_mapping(uint16_t vm_id)
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{
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return &vm_epc_maps[0][vm_id];
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}
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int32_t init_sgx(void)
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{
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if (pcpu_has_cap(X86_FEATURE_SGX)) {
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if ((msr_read(MSR_IA32_FEATURE_CONTROL) & SGX_OPTED_IN) == SGX_OPTED_IN){
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init_sgx_ret = partition_epc();
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if (init_sgx_ret != 0) {
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pr_err("Please change SGX/PRM setting in BIOS or EPC setting in VM config");
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}
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}
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}
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return init_sgx_ret;
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}
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bool is_vsgx_supported(uint16_t vm_id)
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{
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return ((init_sgx_ret == 0) && (vm_epc_maps[0][vm_id].size != 0U));
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}
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