52 lines
1.7 KiB
C
52 lines
1.7 KiB
C
/*
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* Copyright (C) 2018 Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef BOOT_CTX_H
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#define BOOT_CTX_H
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#ifdef ASSEMBLER
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#define BOOT_CTX_CR0_OFFSET 176
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#define BOOT_CTX_CR3_OFFSET 192
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#define BOOT_CTX_CR4_OFFSET 184
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#define BOOT_CTX_IDT_OFFSET 144
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#define BOOT_CTX_GDT_OFFSET 128
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#define BOOT_CTX_LDT_SEL_OFFSET 280
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#define BOOT_CTX_TR_SEL_OFFSET 282
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#define BOOT_CTX_CS_SEL_OFFSET 268
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#define BOOT_CTX_SS_SEL_OFFSET 270
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#define BOOT_CTX_DS_SEL_OFFSET 272
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#define BOOT_CTX_ES_SEL_OFFSET 274
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#define BOOT_CTX_FS_SEL_OFFSET 276
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#define BOOT_CTX_GS_SEL_OFFSET 278
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#define BOOT_CTX_CS_AR_OFFSET 248
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#define BOOT_CTX_CS_LIMIT_OFFSET 252
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#define BOOT_CTX_EFER_LOW_OFFSET 200
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#define BOOT_CTX_EFER_HIGH_OFFSET 204
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#define SIZE_OF_BOOT_CTX 296
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#else
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#define BOOT_CTX_CR0_OFFSET 176U
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#define BOOT_CTX_CR3_OFFSET 192U
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#define BOOT_CTX_CR4_OFFSET 184U
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#define BOOT_CTX_IDT_OFFSET 144U
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#define BOOT_CTX_GDT_OFFSET 128U
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#define BOOT_CTX_LDT_SEL_OFFSET 280U
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#define BOOT_CTX_TR_SEL_OFFSET 282U
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#define BOOT_CTX_CS_SEL_OFFSET 268U
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#define BOOT_CTX_SS_SEL_OFFSET 270U
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#define BOOT_CTX_DS_SEL_OFFSET 272U
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#define BOOT_CTX_ES_SEL_OFFSET 274U
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#define BOOT_CTX_FS_SEL_OFFSET 276U
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#define BOOT_CTX_GS_SEL_OFFSET 278U
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#define BOOT_CTX_CS_AR_OFFSET 248U
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#define BOOT_CTX_CS_LIMIT_OFFSET 252U
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#define BOOT_CTX_EFER_LOW_OFFSET 200U
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#define BOOT_CTX_EFER_HIGH_OFFSET 204U
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#define SIZE_OF_BOOT_CTX 296U
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struct acrn_vcpu_regs;
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extern struct acrn_vcpu_regs boot_context;
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#endif /* ASSEMBLER */
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#endif /* BOOT_CTX_H */
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