267 lines
6.3 KiB
C
267 lines
6.3 KiB
C
/*
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* Copyright (C) 2018 Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <types.h>
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#include <logmsg.h>
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#include <io.h>
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#include <spinlock.h>
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#include <cpu_caps.h>
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#include "pci.h"
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#include "vtd.h"
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#include "acpi.h"
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struct find_iter_args {
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uint32_t i;
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struct acpi_dmar_hardware_unit *res;
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};
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typedef int32_t (*dmar_iter_t)(struct acpi_dmar_header*, void*);
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static uint32_t dmar_unit_cnt;
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static struct dmar_drhd drhd_info_array[MAX_DRHDS];
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static struct dmar_dev_scope drhd_dev_scope[MAX_DRHDS][MAX_DRHD_DEVSCOPES];
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static void *get_dmar_table(void)
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{
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return get_acpi_tbl(ACPI_SIG_DMAR);
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}
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static void
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dmar_iterate_tbl(dmar_iter_t iter, void *arg)
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{
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struct acpi_table_dmar *dmar_tbl;
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struct acpi_dmar_header *dmar_header;
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char *ptr, *ptr_end;
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dmar_tbl = (struct acpi_table_dmar *)get_dmar_table();
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ASSERT(dmar_tbl != NULL, "");
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ptr = (char *)dmar_tbl + sizeof(*dmar_tbl);
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ptr_end = (char *)dmar_tbl + dmar_tbl->header.length;
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for (;;) {
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if (ptr >= ptr_end)
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break;
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dmar_header = (struct acpi_dmar_header *)ptr;
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if (dmar_header->length <= 0) {
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pr_err("drhd: corrupted DMAR table, l %d\n",
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dmar_header->length);
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break;
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}
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ptr += dmar_header->length;
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if (!iter(dmar_header, arg))
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break;
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}
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}
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static int32_t
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drhd_count_iter(struct acpi_dmar_header *dmar_header, __unused void *arg)
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{
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if (dmar_header->type == ACPI_DMAR_TYPE_HARDWARE_UNIT)
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dmar_unit_cnt++;
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return 1;
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}
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static int32_t
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drhd_find_iter(struct acpi_dmar_header *dmar_header, void *arg)
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{
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struct find_iter_args *args;
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int32_t ret = 1;
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if (dmar_header->type == ACPI_DMAR_TYPE_HARDWARE_UNIT){
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args = arg;
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if (args->i == 0U) {
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args->res = (struct acpi_dmar_hardware_unit *)dmar_header;
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ret = 0;
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}
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else{
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args->i--;
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ret = 1;
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}
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}
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return ret;
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}
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static struct acpi_dmar_hardware_unit *
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drhd_find_by_index(uint32_t idx)
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{
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struct find_iter_args args;
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args.i = idx;
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args.res = NULL;
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dmar_iterate_tbl(drhd_find_iter, &args);
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return args.res;
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}
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static uint8_t get_secondary_bus(uint8_t bus, uint8_t dev, uint8_t func)
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{
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uint32_t data;
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pio_write32(PCI_CFG_ENABLE | (bus << 16U) | (dev << 11U) |
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(func << 8U) | 0x18U, PCI_CONFIG_ADDR);
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data = pio_read32(PCI_CONFIG_DATA);
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return (data >> 8U) & 0xffU;
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}
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static union pci_bdf
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dmar_path_bdf(int32_t path_len, int32_t busno,
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const struct acpi_dmar_pci_path *path)
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{
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int32_t i;
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union pci_bdf dmar_bdf;
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dmar_bdf.bits.b = (uint8_t)busno;
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dmar_bdf.bits.d = path->device;
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dmar_bdf.bits.f = path->function;
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for (i = 1; i < path_len; i++) {
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dmar_bdf.bits.b = get_secondary_bus(dmar_bdf.bits.b, dmar_bdf.bits.d, dmar_bdf.bits.f);
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dmar_bdf.bits.d = path[i].device;
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dmar_bdf.bits.f = path[i].function;
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}
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return dmar_bdf;
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}
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static int32_t
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handle_dmar_devscope(struct dmar_dev_scope *dev_scope,
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void *addr, int32_t remaining)
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{
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int32_t path_len;
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union pci_bdf dmar_bdf;
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struct acpi_dmar_pci_path *path;
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struct acpi_dmar_device_scope *apci_devscope = addr;
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if (remaining < (int32_t)sizeof(struct acpi_dmar_device_scope))
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return -1;
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if (remaining < apci_devscope->length)
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return -1;
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path = (struct acpi_dmar_pci_path *)(apci_devscope + 1);
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path_len = (apci_devscope->length -
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sizeof(struct acpi_dmar_device_scope)) /
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sizeof(struct acpi_dmar_pci_path);
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dmar_bdf = dmar_path_bdf(path_len, apci_devscope->bus, path);
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dev_scope->id = apci_devscope->enumeration_id;
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dev_scope->type = apci_devscope->entry_type;
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dev_scope->bus = dmar_bdf.fields.bus;
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dev_scope->devfun = dmar_bdf.fields.devfun;
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return apci_devscope->length;
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}
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static uint32_t
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get_drhd_dev_scope_cnt(struct acpi_dmar_hardware_unit *drhd)
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{
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struct acpi_dmar_device_scope *scope;
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char *start;
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char *end;
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uint32_t count = 0;
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start = (char *)drhd + sizeof(struct acpi_dmar_hardware_unit);
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end = (char *)drhd + drhd->header.length;
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while (start < end) {
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scope = (struct acpi_dmar_device_scope *)start;
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if ((scope->entry_type != ACPI_DMAR_SCOPE_TYPE_NOT_USED) &&
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(scope->entry_type < ACPI_DMAR_SCOPE_TYPE_RESERVED))
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count++;
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start += scope->length;
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}
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return count;
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}
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/**
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* @Application constraint: The dedicated DMAR unit for Intel integrated GPU
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* shall be available on the physical platform.
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*/
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static int32_t
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handle_one_drhd(struct acpi_dmar_hardware_unit *acpi_drhd,
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struct dmar_drhd *drhd)
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{
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struct dmar_dev_scope *dev_scope;
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struct acpi_dmar_device_scope *ads;
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int32_t remaining, consumed;
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char *cp;
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uint32_t dev_count;
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drhd->segment = acpi_drhd->segment;
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drhd->flags = acpi_drhd->flags;
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drhd->reg_base_addr = acpi_drhd->address;
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dev_count = get_drhd_dev_scope_cnt(acpi_drhd);
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ASSERT(dev_count <= MAX_DRHD_DEVSCOPES, "parsed dev_count > MAX_DRHD_DEVSCOPES");
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drhd->dev_cnt = dev_count;
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remaining = acpi_drhd->header.length -
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sizeof(struct acpi_dmar_hardware_unit);
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dev_scope = drhd->devices;
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while (remaining > 0) {
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cp = (char *)acpi_drhd + acpi_drhd->header.length - remaining;
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consumed = handle_dmar_devscope(dev_scope, cp, remaining);
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/* Disable GPU IOMMU due to gvt-d hasn’t been enabled on APL yet. */
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if (is_apl_platform()) {
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if (((drhd->segment << 16U) |
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(dev_scope->bus << 8U) |
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dev_scope->devfun) == CONFIG_GPU_SBDF) {
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drhd->ignore = true;
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}
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}
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if (consumed <= 0)
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break;
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remaining -= consumed;
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/* skip IOAPIC & HPET */
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ads = (struct acpi_dmar_device_scope *)cp;
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if ((ads->entry_type != ACPI_DMAR_SCOPE_TYPE_NOT_USED) &&
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(ads->entry_type < ACPI_DMAR_SCOPE_TYPE_RESERVED)) {
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dev_scope++;
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}
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else
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pr_dbg("drhd: skip dev_scope type %d",
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ads->entry_type);
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}
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return 0;
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}
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int32_t parse_dmar_table(struct dmar_info *plat_dmar_info)
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{
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uint32_t i;
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struct acpi_dmar_hardware_unit *acpi_drhd;
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/* find out how many dmar units */
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dmar_iterate_tbl(drhd_count_iter, NULL);
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ASSERT(dmar_unit_cnt <= MAX_DRHDS, "parsed dmar_unit_cnt > MAX_DRHDS");
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plat_dmar_info->drhd_count = dmar_unit_cnt;
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plat_dmar_info->drhd_units = drhd_info_array;
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for (i = 0U; i < dmar_unit_cnt; i++) {
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acpi_drhd = drhd_find_by_index(i);
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if (acpi_drhd == NULL)
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continue;
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if (acpi_drhd->flags & DRHD_FLAG_INCLUDE_PCI_ALL_MASK)
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ASSERT((i + 1U) == dmar_unit_cnt,
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"drhd with flags set should be the last one");
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plat_dmar_info->drhd_units[i].devices = drhd_dev_scope[i];
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handle_one_drhd(acpi_drhd, &(plat_dmar_info->drhd_units[i]));
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}
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return 0;
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}
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