232 lines
7.8 KiB
C
232 lines
7.8 KiB
C
/*
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* This file is provided under a dual BSD/GPLv2 license. When using or
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* redistributing this file, you may do so under either license.
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*
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* GPL LICENSE SUMMARY
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*
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* Copyright (c) 2017 Intel Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* BSD LICENSE
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*
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* Copyright (C) 2017 Intel Corporation. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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/**
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* @file vhm_ioctl_defs.h
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*
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* @brief Virtio and Hypervisor Module definition for ioctl to user space
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*/
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#ifndef _VHM_IOCTL_DEFS_H_
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#define _VHM_IOCTL_DEFS_H_
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/* Commmon structures for ACRN/VHM/DM */
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#include "acrn_common.h"
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/*
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* Commmon IOCTL ID defination for VHM/DM
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*/
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#define _IC_ID(x, y) (((x)<<24)|(y))
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#define IC_ID 0x43UL
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/* General */
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#define IC_ID_GEN_BASE 0x0UL
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#define IC_GET_API_VERSION _IC_ID(IC_ID, IC_ID_GEN_BASE + 0x00)
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/* VM management */
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#define IC_ID_VM_BASE 0x10UL
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#define IC_CREATE_VM _IC_ID(IC_ID, IC_ID_VM_BASE + 0x00)
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#define IC_DESTROY_VM _IC_ID(IC_ID, IC_ID_VM_BASE + 0x01)
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#define IC_START_VM _IC_ID(IC_ID, IC_ID_VM_BASE + 0x02)
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#define IC_PAUSE_VM _IC_ID(IC_ID, IC_ID_VM_BASE + 0x03)
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#define IC_CREATE_VCPU _IC_ID(IC_ID, IC_ID_VM_BASE + 0x04)
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#define IC_RESET_VM _IC_ID(IC_ID, IC_ID_VM_BASE + 0x05)
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#define IC_SET_VCPU_REGS _IC_ID(IC_ID, IC_ID_VM_BASE + 0x06)
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/* IRQ and Interrupts */
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#define IC_ID_IRQ_BASE 0x20UL
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#define IC_ASSERT_IRQLINE _IC_ID(IC_ID, IC_ID_IRQ_BASE + 0x00)
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#define IC_DEASSERT_IRQLINE _IC_ID(IC_ID, IC_ID_IRQ_BASE + 0x01)
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#define IC_PULSE_IRQLINE _IC_ID(IC_ID, IC_ID_IRQ_BASE + 0x02)
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#define IC_INJECT_MSI _IC_ID(IC_ID, IC_ID_IRQ_BASE + 0x03)
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#define IC_VM_INTR_MONITOR _IC_ID(IC_ID, IC_ID_IRQ_BASE + 0x04)
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/* DM ioreq management */
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#define IC_ID_IOREQ_BASE 0x30UL
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#define IC_SET_IOREQ_BUFFER _IC_ID(IC_ID, IC_ID_IOREQ_BASE + 0x00)
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#define IC_NOTIFY_REQUEST_FINISH _IC_ID(IC_ID, IC_ID_IOREQ_BASE + 0x01)
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#define IC_CREATE_IOREQ_CLIENT _IC_ID(IC_ID, IC_ID_IOREQ_BASE + 0x02)
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#define IC_ATTACH_IOREQ_CLIENT _IC_ID(IC_ID, IC_ID_IOREQ_BASE + 0x03)
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#define IC_DESTROY_IOREQ_CLIENT _IC_ID(IC_ID, IC_ID_IOREQ_BASE + 0x04)
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/* Guest memory management */
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#define IC_ID_MEM_BASE 0x40UL
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/* IC_ALLOC_MEMSEG not used */
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#define IC_ALLOC_MEMSEG _IC_ID(IC_ID, IC_ID_MEM_BASE + 0x00)
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#define IC_SET_MEMSEG _IC_ID(IC_ID, IC_ID_MEM_BASE + 0x01)
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#define IC_UNSET_MEMSEG _IC_ID(IC_ID, IC_ID_MEM_BASE + 0x02)
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/* PCI assignment*/
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#define IC_ID_PCI_BASE 0x50UL
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#define IC_ASSIGN_PTDEV _IC_ID(IC_ID, IC_ID_PCI_BASE + 0x00)
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#define IC_DEASSIGN_PTDEV _IC_ID(IC_ID, IC_ID_PCI_BASE + 0x01)
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#define IC_VM_PCI_MSIX_REMAP _IC_ID(IC_ID, IC_ID_PCI_BASE + 0x02)
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#define IC_SET_PTDEV_INTR_INFO _IC_ID(IC_ID, IC_ID_PCI_BASE + 0x03)
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#define IC_RESET_PTDEV_INTR_INFO _IC_ID(IC_ID, IC_ID_PCI_BASE + 0x04)
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/* Power management */
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#define IC_ID_PM_BASE 0x60UL
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#define IC_PM_GET_CPU_STATE _IC_ID(IC_ID, IC_ID_PM_BASE + 0x00)
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#define VM_MEMMAP_SYSMEM 0
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#define VM_MMIO 1
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/* VHM eventfd */
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#define IC_ID_EVENT_BASE 0x70UL
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#define IC_EVENT_IOEVENTFD _IC_ID(IC_ID, IC_ID_EVENT_BASE + 0x00)
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#define IC_EVENT_IRQFD _IC_ID(IC_ID, IC_ID_EVENT_BASE + 0x01)
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/**
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* struct vm_memmap - EPT memory mapping info for guest
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*/
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struct vm_memmap {
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/** @type: memory mapping type */
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uint32_t type;
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/** @using_vma: using vma_base to get vm0_gpa,
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* only for type == VM_MEMMAP_SYSMEM
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*/
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uint32_t using_vma;
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/** @gpa: user OS guest physical start address of memory mapping */
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uint64_t gpa;
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/** union */
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union {
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/** @hpa: host physical start address of memory,
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* only for type == VM_MMIO
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*/
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uint64_t hpa;
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/** @vma_base: service OS user virtual start address of
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* memory, only for type == VM_MEMMAP_SYSMEM &&
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* using_vma == true
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*/
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uint64_t vma_base;
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};
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/** @len: the length of memory range mapped */
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uint64_t len; /* mmap length */
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/** @prot: memory mapping attribute */
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uint32_t prot; /* RWX */
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};
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/**
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* struct ic_ptdev_irq - pass thru device irq data structure
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*/
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struct ic_ptdev_irq {
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#define IRQ_INTX 0
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#define IRQ_MSI 1
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#define IRQ_MSIX 2
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/** @type: irq type */
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uint32_t type;
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/** @virt_bdf: virtual bdf description of pass thru device */
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uint16_t virt_bdf; /* IN: Device virtual BDF# */
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/** @phy_bdf: physical bdf description of pass thru device */
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uint16_t phys_bdf; /* IN: Device physical BDF# */
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/** union */
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union {
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/** struct intx - info of IOAPIC/PIC interrupt */
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struct {
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/** @virt_pin: virtual IOAPIC pin */
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uint32_t virt_pin;
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/** @phys_pin: physical IOAPIC pin */
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uint32_t phys_pin;
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/** @pic_pin: PIC pin */
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uint32_t is_pic_pin;
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} intx;
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/** struct msix - info of MSI/MSIX interrupt */
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struct {
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/* Keep this filed on top of msix */
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/** @vector_cnt: vector count of MSI/MSIX */
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uint32_t vector_cnt;
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/** @table_size: size of MSIX table(round up to 4K) */
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uint32_t table_size;
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/** @table_paddr: physical address of MSIX table */
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uint64_t table_paddr;
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} msix;
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};
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};
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/**
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* struct ioreq_notify - data strcture to notify hypervisor ioreq is handled
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*
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* @client_id: client id to identify ioreq client
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* @vcpu: identify the ioreq submitter
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*/
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struct ioreq_notify {
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int32_t client_id;
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uint32_t vcpu;
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};
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/**
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* struct api_version - data structure to track VHM API version
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*
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* @major_version: major version of VHM API
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* @minor_version: minor version of VHM API
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*/
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struct api_version {
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uint32_t major_version;
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uint32_t minor_version;
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};
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#define ACRN_IOEVENTFD_FLAG_PIO 0x01
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#define ACRN_IOEVENTFD_FLAG_DATAMATCH 0x02
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#define ACRN_IOEVENTFD_FLAG_DEASSIGN 0x04
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struct acrn_ioeventfd {
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int32_t fd;
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uint32_t flags;
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uint64_t addr;
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uint32_t len;
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uint32_t reserved;
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uint64_t data;
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};
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#define ACRN_IRQFD_FLAG_DEASSIGN 0x01
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struct acrn_irqfd {
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int32_t fd;
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uint32_t flags;
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struct acrn_msi_entry msi;
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};
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#endif /* VHM_IOCTL_DEFS_H */
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